这篇博文主要记录在写异步FIFO中遇到的问题,
具体的异步的FIFO的时序可以参考其他文章。
本博文的异步FIFO的思路(调用FPGA的FIFO IP核):
(1)当写操作写满,或者读操作读空后,需要等待最慢周期的60个周期,因此需要设计一个二段式的状态机,分为等待状态和FIFO读写状态;
always @(*)
begin
case(write_state)
W_IDLE:
begin
if ( write_wait_counter == 8'd79)
begin
next_write_state <= W_FIFO;
end
else
begin
next_write_state <= W_IDLE;
end
end
W_FIFO:
begin
next_write_state <= W_FIFO;
end
default:
begin
next_write_state <= W_IDLE;
end
endcase
end
(2)在等待状态中,需要计数周期,因此需要一个always块来计数;
// counter 计数
always @(posedge wr_clk or negedge rst)
begin
if (! rst)
begin
// reset
write_wait_counter <= 8'd0;
end
else if ( write_state == W_IDLE)
begin
write_wait_counter <= write_wait_counter +1'd1;
end
else
begin
write_wait_counter <= 8'd0;
end
end
(3)写入或读出的状态, 在状态机中不能直接赋值,因此创建一个新的寄存器用来存储状态,需要一个always块把状态连接起来;
always @(posedge wr_clk or negedge rst)
begin
if ( ! rst)
begin
// reset
write_state <= W_IDLE;
end
else
begin
write_state <= next_write_state;
end
end
(4)使能信号的设定,当状态处于读写状态时,使能置1,高有效;当状态处于其他状态时,置1,无效; 因此采用三目运算符;
// write enable signal when writing data is full, full will be set to 1
assign wr_en = (write_state == W_FIFO) ? ~full : 1'b0 ;
(5)写入FIFO数据,使能有效时,data+1
// write fifo data
always @(posedge wr_clk or negedge rst)
begin
if (! rst)
begin
// reset
write_data <= 16'd0;
end
else if (wr_en)<