基于FPGA的有符号位全并行移位相加乘法器设计

最新推荐文章于 2024-07-08 23:22:01 发布

墨漓_lyl

最新推荐文章于 2024-07-08 23:22:01 发布

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分类专栏：基于FPGA的数字信号处理文章标签： fpga 数字信号处理

本文链接：https://blog.csdn.net/qq_42025108/article/details/118253679

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1.二进制乘法原理介绍

理论部分引用于书籍：基于FPGA的数字信号处理[高亚军编著]
二进制乘法原理与十进制乘法原理类似，都是将乘数的每一位分别与被乘数相乘，除此之外，二进制乘法还有其自身的特点，这对于硬件设计极为关键。
二进制乘法可分为两种情况：无符号数乘法和有符号数乘法。
无符号数乘法示例如下：
在这里插入图片描述
有符号数的正数乘负数示例如下：

有符号数的负数乘负数示例如下：

由上述示例，我们可以得出结论，若两乘数的位宽分别位a，b，则：
1.无论是有符号数相乘还是无符号数相乘，其乘积的位宽必定位a+b；
2.如果被乘数和乘数均为有符号数，那么相乘之前首先要进行符号位扩展，将被乘数和乘数均扩展位a+b位。

2.基于移位相加的乘法器

其硬件结构如下图所示：
在这里插入图片描述

3.乘法器verilog源代码

该乘法器为24位有符号数据与16为有符号数据相乘的乘法器，代码如下：

`timescale 1ns / 1ps
module multiply24_16(
	input	wire signed[23:0]		i_data1	,  	 
	input	wire signed[15:0]		i_data2	,	

	output	wire signed[39:0]		o_data 		 

	);

wire [39:0] data_ext1;
wire [39:0] data_ext2;

wire[39:0]	m_data0;
wire[39:0]	m_data1;
wire[39:0]	m_data2;
wire[39:0]	m_data3;
wire[39:0]	m_data4;
wire[39:0]	m_data5;
wire[39:0]	m_data6;
wire[39:0]	m_data7;
wire[39:0]	m_data8;
wire[39:0]	m_data9;
wire[39:0]	m_data10;
wire[39:0]	m_data11;
wire[39:0]	m_data12;
wire[39:0]	m_data13;
wire[39:0]	m_data14;
wire[39:0]	m_data15;
wire[39:0]	m_data16;
wire[39:0]	m_data17;
wire[39:0]	m_data18;
wire[39:0]	m_data19;
wire[39:0]	m_data20;
wire[39:0]	m_data21;
wire[39:0]	m_data22;
wire[39:0]	m_data23;
wire[39:0]	m_data24;
wire[39:0]	m_data25;
wire[39:0]	m_data26;
wire[39:0]	m_data27;
wire[39:0]	m_data28;
wire[39:0]	m_data29;
wire[39:0]	m_data30;
wire[39:0]	m_data31;
wire[39:0]	m_data32;
wire[39:0]	m_data33;
wire[39:0]	m_data34;
wire[39:0]	m_data35;
wire[39:0]	m_data36;
wire[39:0]	m_data37;
wire[39:0]	m_data38;
wire[39:0]	m_data39;

assign data_ext1 = {{16{i_data1[23]}},i_data1};
assign data_ext2 = {{24{i_data2[15]}},i_data2};

assign m_data0 	= data_ext2[0 ]?(data_ext1    ):48'd0;
assign m_data1 	= data_ext2[1 ]?(data_ext1<<1 ):48'd0;
assign m_data2 	= data_ext2[2 ]?(data_ext1<<2 ):48'd0;
assign m_data3 	= data_ext2[3 ]?(data_ext1<<3 ):48'd0;
assign m_data4 	= data_ext2[4 ]?(data_ext1<<4 ):48'd0;
assign m_data5 	= data_ext2[5 ]?(data_ext1<<5 ):48'd0;
assign m_data6 	= data_ext2[6 ]?(data_ext1<<6 ):48'd0;
assign m_data7 	= data_ext2[7 ]?(data_ext1<<7 ):48'd0;
assign m_data8 	= data_ext2[8 ]?(data_ext1<<8 ):48'd0;
assign m_data9 	= data_ext2[9 ]?(data_ext1<<9 ):48'd0;
assign m_data10 = data_ext2[10]?(data_ext1<<10):48'd0;
assign m_data11 = data_ext2[11]?(data_ext1<<11):48'd0;
assign m_data12 = data_ext2[12]?(data_ext1<<12):48'd0;
assign m_data13 = data_ext2[13]?(data_ext1<<13):48'd0;
assign m_data14 = data_ext2[14]?(data_ext1<<14):48'd0;
assign m_data15 = data_ext2[15]?(data_ext1<<15):48'd0;
assign m_data16 = data_ext2[16]?(data_ext1<<16):48'd0;
assign m_data17 = data_ext2[17]?(data_ext1<<17):48'd0;
assign m_data18 = data_ext2[18]?(data_ext1<<18):48'd0;
assign m_data19 = data_ext2[19]?(data_ext1<<19):48'd0;
assign m_data20 = data_ext2[20]?(data_ext1<<20):48'd0;
assign m_data21 = data_ext2[21]?(data_ext1<<21):48'd0;
assign m_data22 = data_ext2[22]?(data_ext1<<22):48'd0;
assign m_data23 = data_ext2[23]?(data_ext1<<23):48'd0;
assign m_data24 = data_ext2[24]?(data_ext1<<24):48'd0;
assign m_data25 = data_ext2[25]?(data_ext1<<25):48'd0;
assign m_data26 = data_ext2[26]?(data_ext1<<26):48'd0;
assign m_data27 = data_ext2[27]?(data_ext1<<27):48'd0;
assign m_data28 = data_ext2[28]?(data_ext1<<28):48'd0;
assign m_data29 = data_ext2[29]?(data_ext1<<29):48'd0;
assign m_data30 = data_ext2[30]?(data_ext1<<30):48'd0;
assign m_data31 = data_ext2[31]?(data_ext1<<31):48'd0;
assign m_data32 = data_ext2[32]?(data_ext1<<32):48'd0;
assign m_data33 = data_ext2[33]?(data_ext1<<33):48'd0;
assign m_data34 = data_ext2[34]?(data_ext1<<34):48'd0;
assign m_data35 = data_ext2[35]?(data_ext1<<35):48'd0;
assign m_data36 = data_ext2[36]?(data_ext1<<36):48'd0;
assign m_data37 = data_ext2[37]?(data_ext1<<37):48'd0;
assign m_data38 = data_ext2[38]?(data_ext1<<38):48'd0;
assign m_data39 = data_ext2[39]?(data_ext1<<39):48'd0;
assign m_data40 = data_ext2[40]?(data_ext1<<40):48'd0;
assign m_data41 = data_ext2[41]?(data_ext1<<41):48'd0;
assign m_data42 = data_ext2[42]?(data_ext1<<42):48'd0;
assign m_data43 = data_ext2[43]?(data_ext1<<43):48'd0;
assign m_data44 = data_ext2[44]?(data_ext1<<44):48'd0;
assign m_data45 = data_ext2[45]?(data_ext1<<45):48'd0;
assign m_data46 = data_ext2[46]?(data_ext1<<46):48'd0;
assign m_data47 = data_ext2[47]?(data_ext1<<47):48'd0;
assign m_data24 = data_ext2[24]?(data_ext1<<24):48'd0;
assign m_data25 = data_ext2[25]?(data_ext1<<25):48'd0;
assign m_data26 = data_ext2[26]?(data_ext1<<26):48'd0;
assign m_data27 = data_ext2[27]?(data_ext1<<27):48'd0;
assign m_data28 = data_ext2[28]?(data_ext1<<28):48'd0;
assign m_data29 = data_ext2[29]?(data_ext1<<29):48'd0;
assign m_data30 = data_ext2[30]?(data_ext1<<30):48'd0;
assign m_data31 = data_ext2[31]?(data_ext1<<31):48'd0;
assign m_data32 = data_ext2[32]?(data_ext1<<32):48'd0;
assign m_data33 = data_ext2[33]?(data_ext1<<33):48'd0;
assign m_data34 = data_ext2[34]?(data_ext1<<34):48'd0;
assign m_data35 = data_ext2[35]?(data_ext1<<35):48'd0;
assign m_data36 = data_ext2[36]?(data_ext1<<36):48'd0;
assign m_data37 = data_ext2[37]?(data_ext1<<37):48'd0;
assign m_data38 = data_ext2[38]?(data_ext1<<38):48'd0;
assign m_data39 = data_ext2[39]?(data_ext1<<39):48'd0;


assign o_data = m_data0 + m_data1 + m_data2 + m_data3 + m_data4 + m_data5 + m_data6 + m_data7 + m_data8 + m_data9 + m_data10 + m_data11 + m_data12 + m_data13 + m_data14 + m_data15 + m_data16 + m_data17 + m_data18 + m_data19 + m_data20 + m_data21 + m_data22 + m_data23 + m_data24  + m_data25  + m_data26  + m_data27  + m_data28  + m_data29  + m_data30  + m_data31  + m_data32  + m_data33  + m_data34  + m_data35  + m_data36  + m_data37  + m_data38  + m_data39;

endmodule