hdlbits答案：Thermostat、Popcount3、Gatesv、Gatesv100、Mux2to1、Mux2to1v、Mux9to1v、Mux256to1、Mux256to1v、Hadd

Thermostat

A heating/cooling thermostat controls both a heater (during winter) and an air conditioner (during summer). Implement a circuit that will turn on and off the heater, air conditioning, and blower fan as appropriate.

The thermostat can be in one of two modes: heating (mode = 1) and cooling (mode = 0). In heating mode, turn the heater on when it is too cold (too_cold = 1) but do not use the air conditioner. In cooling mode, turn the air conditioner on when it is too hot (too_hot = 1), but do not turn on the heater. When the heater or air conditioner are on, also turn on the fan to circulate the air. In addition, the user can also request the fan to turn on (fan_on = 1), even if the heater and air conditioner are off.

Try to use only assign statements, to see whether you can translate a problem description into a collection of logic gates.

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 
always @(*)begin
	if(mode==1'b1&too_cold==1'b1)begin 
		heater=1'b1;
		aircon=1'b0;
	end 
	else if (mode==1'b0&&too_hot==1'b1)begin 
		heater=1'b0;
		aircon=1'b1;	
	end
	else begin
		heater=1'b0;
		aircon=1'b0;	
	end 	
end 
always @(*)begin
	if(fan_on==1'b1)
		fan=1'b1;
	else if(heater==1||aircon==1)
		fan=1'b1;
	else 
		fan=0;
end 
endmodule

Popcount3

A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 3-bit input vector.

module top_module( 
    input [2:0] in,
    output [1:0] out );
always@(*)begin
	casez(in)
		3'b000:	out=3'd0;
		3'b001: out=3'd1;
		3'b010: out=3'd1;
		3'b011: out=3'd2;
		3'b100: out=3'd1;
		3'b101: out=3'd2;
		3'b110: out=3'd2;
		3'b111: out=3'd3;
		default:out=3'd0;
	endcase 
end 
endmodule

或者以下代码也可：

module top_module( 
    input [2:0] in,
    output [1:0] out );
always@(*)begin
	casez(in)
		3'b001,3'b010,3'b100: out=3'd1;
		3'b011,3'b101,3'b110: out=3'd2;
		3'b111: out=3'd3;
		default:out=3'd0;
	endcase 
end 
endmodule

Gatesv

You are given a four-bit input vector in[3:0]. We want to know some relationships between each bit and its neighbour:

out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left (higher index) are '1'. For example, out_both[2] should indicate if in[2] and in[3] are both 1. Since in[3] has no neighbour to the left, the answer is obvious so we don't need to know out_both[3].

out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are '1'. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don't need to know out_any[0].

out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[2] should indicate if in[2] is different from in[3]. For this part, treat the vector as wrapping around, so in[3]'s neighbour to the left is in[0].

module top_module( 
    input [3:0] in,
    output [2:0] out_both,
    output [3:1] out_any,
    output [3:0] out_different );
assign out_both[2]=in[2]&in[3];
assign out_both[1]=in[1]&in[2];
assign out_both[0]=in[0]&in[1];
assign out_any[3]=in[3]|in[2];
assign out_any[2]=in[2]|in[1];
assign out_any[1]=in[1]|in[0];
assign out_different[3]=in[3]^in[0];
assign out_different[2]=in[2]^in[3];
assign out_different[1]=in[1]^in[2];
assign out_different[0]=in[0]^in[1];
endmodule

Gatesv100

See also the shorter version: Gates and vectors.

You are given a 100-bit input vector in[99:0]. We want to know some relationships between each bit and its neighbour:

• out_both: Each bit of this output vector should indicate whether both the corresponding input bit and its neighbour to the left are '1'. For example, out_both[98] should indicate if in[98] and in[99] are both 1. Since in[99] has no neighbour to the left, the answer is obvious so we don't need to know out_both[99].
• out_any: Each bit of this output vector should indicate whether any of the corresponding input bit and its neighbour to the right are '1'. For example, out_any[2] should indicate if either in[2] or in[1] are 1. Since in[0] has no neighbour to the right, the answer is obvious so we don't need to know out_any[0].
• out_different: Each bit of this output vector should indicate whether the corresponding input bit is different from its neighbour to the left. For example, out_different[98] should indicate if in[98] is different from in[99]. For this part, treat the vector as wrapping around, so in[99]'s neighbour to the left is in[0].
   

  module top_module( 
      input [99:0] in,
      output [98:0] out_both,
      output [99:1] out_any,
      output [99:0] out_different );
  	genvar i;
      generate
  		for(i=0;i<100;i++) begin:out
  		if(i==0)begin
  			assign out_both[0]=in[0]&in[1];
  			assign out_different[0]=in[0]^in[1];
  		end
  		else if(i==99)begin
  			assign out_any[99]=in[99]|in[98];
  			assign out_different[99]=in[99]^in[0];
  		end	
  		else begin 
  			assign out_both[i]=in[i]&in[i+1];
  			assign out_any[i]=in[i]|in[i-1];
  			assign out_different[i]=in[i]^in[i+1];
  		end 
  		end
  	endgenerate
  endmodule
  

  这道题和上一个题很相似，主要是考虑下i==0和i==99这两种情况下，别的直接用for就可以。
  Mux2to1
  Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

module top_module( 
    input a, b, sel,
    output out ); 
	assign out=sel?b:a;
endmodule

Mux2to1v

Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );
    assign out = sel?b:a;
endmodule

Mux9to1v

Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'.

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
always@(*)begin 
	case(sel)
		4'd0:out=a;
		4'd1:out=b;
		4'd2:out=c;
		4'd3:out=d;
		4'd4:out=e;
		4'd5:out=f;
		4'd6:out=g;
		4'd7:out=h;
		4'd8:out=i;
		default	:out=16'hffff;	
    endcase
end 
endmodule

Mux256to1

Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.

这道题最初竟然想着用for语句，确实想偏题了

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );
    assign  out=in[sel];
endmodule

Mux256to1v

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
     assign out = {in[sel*4+3],in[sel*4+2],in[sel*4+1],in[sel*4]};
endmodule

直接用in[4*sel+3,4*sel]报错

Hadd

Create a half adder. A half adder adds two bits (with no carry-in) and produces a sum and carry-out.

module top_module( 
    input a, b,
    output cout, sum );
    assign{cout,sum}=a+b;
endmodule