HDLBits-Gatesv100

上一章的问题提升到100个
答案
module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );
integer i,j;
always@(in)
begin
j=100;
for(i=0;i<j-1;i++)
begin
out_both[i] = (in[i+1] == 1 & in[i] == 1)?1:0;
end
for(i=1;i<j;i++)
begin
out_any[i] = (in[i] ==1 | in[i-1] == 1)?1:0;
end
for(i=0;i<j;i++)
begin
if(i == j-1)
out_different[i] = (in[j-1] != in[0])?1:0;
else
out_different[i] = (in[i+1] != in[i])?1:0;
end
end

endmodule