VHDL二选一选择器代码及其仿真代码

二选一选择器
代码
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test2 is
Port ( a,b,sel:in BIT;y:out bit);
end test2;

architecture Behavioral of test2 is
signal m ,n:bit;
begin
process(a,b,sel)

m<=a and sel;
n<=b and (not sel);
y<=m or n;

end Behavioral;

仿真代码
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity test_bench is
– Port ( );
end test_bench;

architecture Behavioral of test_bench is
component test2 port(
a,b,sel:in BIT;
y:out bit);
end component;
signal a:bit:=‘0’;
signal b:bit:=‘0’;
signal sel:bit:=‘0’;
signal y:bit:=‘0’;
constant clk_period :time :=20 ns;
begin
dut:test2 port map(
a=>a,b=>b,sel=>sel,y=>y
);
process
begin
sel<=‘1’;
wait for 10ns;
sel<=‘0’;
wait for 10ns;
end process;
a<=‘1’;
b<=‘0’;
end Behavioral;