面积换速度：Carry Look-ahead Adder

• A carry-look-ahead adder improves speed by reducing the time required to determine carry bits.
• The “CLA logic” is also the timing critical psth inthe design.
• 面积换速度，3个16bit的CLA来提高一个32bit的CLA
  
• we wiil use three 16-bits adders to design a faster 32-bits adders.
• Low 16-bits adder will output low 16-bits of sum(sum[15:0])
• Two high 16-bits adders have same high 16-bits inputs, but one’s carry_in is 1’b0, another is 1’b1.
• The high 16-bits of sum and carry_out of 32-bits adder will depend on carry_out of the low 16-bits adder
• If carry_out of low 16-bits adder(carry_out_low) is 0/1.
  • high 16-bits of sum will be sum_high_0[15:0]/sum_high_1[15:0]
  • carry_out will be carry_out_high_0/carry_out_high_1
    

And from the different comparisions, we learned higher frequency requires higher gate count.