FPGA开发之SRIO接口回环测试
一、接口部分
s_axis_ireq:发送接口
m_axis_treq:接收接口
m_axis_iresp:接收应答接口
s_axis_tresp:发送应答接口
tvalid : 表示数据有效
tdata : 有效数据,要有HELLO包头
tready : IP核输出,表示可以向其发送数据
tlast : 标志最后一个数据
tuser : ID号,仅tvalid 的第一个时钟周期内有效
tkeep : 固定为8’hFF
二、HELLO包头
见官方手册《PG007》P.76
HELLO格式的包中Size域的值等于传输的字节的总数减1,Size域的有效值范围为0~255字节
RapidIO协议定义了七种事务类型,每种事务类型执行不同的功能。RapidIO包格式中的FTYPE字段与TTYPE字段共同确定了事务的类型
三、外设数据传输
发送外设数据流总体流程是:
- 产生64位数据 :具体多少位依据IP核的配置
-
写s_axis_ireq接口时序 :只提供一种简单的时序,还有另一种多HELLO包传输格式的。注意一定要有包头!!!,tready在接收到包头后会输出1T的电平后拉高,所以包头后紧跟的数据需要多保持1T,具体可以看最后的仿真图;tvalid一定要保持高电平!!!,否则会进入第二种传输格式,本人在此处走了大量弯路。
但是,如果你的数据无法连续,那么就在D0后拉低tvalid,等待有效数据,当再次拉高tvalid后tready依旧会在下1T拉低,之后再有效,详见仿真二。
-
IP核自动通过srio_tx_p和srio_tx_n 发送数据
-
短接srio_tx_p核srio_rx_p 、srio_tx_n 和srio_rx_n
-
抓取m_axis_treq接口输出信号,可以看到包头已被修变,载荷正常
仿真一:数据连续
仿真二:数据不连续,注意在tready拉低时不要丢失数据,这里丢失了3
四、程序
module srio_top(
input clk_125m_p,
input clk_125m_n,
input rstn,
output srio_tx_p,
output srio_tx_n,
input srio_rx_p,
input srio_rx_n
);
reg ireq_tvalid ;
wire ireq_tready ;
reg ireq_tlast ;
reg [63:0] ireq_tdata ;
reg [7:0] ireq_tkeep ;
reg [31:0] ireq_tuser ;
wire treq_tvalid ;
wire treq_tready ;
wire treq_tlast ;
wire [63:0] treq_tdata ;
wire [7:0] treq_tkeep ;
wire [31:0] treq_tuser ;
wire log_clk;
wire log_rst;
reg [7:0] SM_COUNT;
reg [31:0] cnt_interval;
reg [31:0] cnt_sent;
assign treq_tready = 1'b1;
always @(posedge log_clk or posedge log_rst) begin
if(log_rst == 1'b1) begin
ireq_tvalid <= 0;
ireq_tlast <= 0;
ireq_tdata <= 0;
ireq_tkeep <= 8'hff;
ireq_tuser <= 8'd1;
SM_COUNT <= 0;
cnt_sent <= 0;
end
else begin
case (SM_COUNT)
8'd0: begin
if(cnt_interval >= 32'd125_000_000)
SM_COUNT <= 1;
else begin
SM_COUNT <= 0;
ireq_tvalid <= 1'b0;
ireq_tlast <= 1'b0;
end
end
8'd1: begin
ireq_tdata <= 64'h0154_2c80_0000_0007;
SM_COUNT <= 2;
end
8'd2: begin
ireq_tvalid <= 1'b1;
SM_COUNT <= 3;
end
8'd3: begin
ireq_tdata <= 64'h0;
SM_COUNT <= 4;
end
8'd4: begin
ireq_tdata <= ireq_tdata + 64'h01;
if(cnt_sent <= 4'd10)begin
cnt_sent <= cnt_sent + 1;
SM_COUNT <= 4;
end
else begin
SM_COUNT <= 0;
ireq_tlast <= 1;
cnt_sent <= 0;
end
end
default: ;
endcase
end
end
always @(posedge log_clk or posedge log_rst) begin
if(log_rst == 1'b1) begin
cnt_interval <= 32'd0;
end
else if(SM_COUNT == 8'd0) begin
cnt_interval <= cnt_interval + 32'd1;
end
else
cnt_interval <= 32'd0;
end
srio_gen2_0 srio_gen_inst (
.sys_clkp(clk_125m_p), // input wire sys_clkp
.sys_clkn(clk_125m_n), // input wire sys_clkn
.sys_rst(~rstn), // input wire sys_rst
.log_clk_out(log_clk), // output wire log_clk_out
.buf_rst_out( ), // output wire buf_rst_out
.log_rst_out(log_rst), // output wire log_rst_out
.gt_pcs_rst_out( ), // output wire gt_pcs_rst_out
.gt_pcs_clk_out( ), // output wire gt_pcs_clk_out
.cfg_rst_out( ), // output wire cfg_rst_out
.deviceid( ), // output wire [15 : 0] deviceid
.port_decode_error( ), // output wire port_decode_error
.s_axis_ireq_tvalid(ireq_tvalid), // input wire s_axis_ireq_tvalid
.s_axis_ireq_tready(ireq_tready), // output wire s_axis_ireq_tready
.s_axis_ireq_tlast( ireq_tlast), // input wire s_axis_ireq_tlast
.s_axis_ireq_tdata(ireq_tdata), // input wire [63 : 0] s_axis_ireq_tdata
.s_axis_ireq_tkeep(ireq_tkeep), // input wire [7 : 0] s_axis_ireq_tkeep
.s_axis_ireq_tuser(ireq_tuser), // input wire [31 : 0] s_axis_ireq_tuser
.m_axis_iresp_tvalid( ), // output wire m_axis_iresp_tvalid
.m_axis_iresp_tready(0 ), // input wire m_axis_iresp_tready
.m_axis_iresp_tlast( ), // output wire m_axis_iresp_tlast
.m_axis_iresp_tdata( ), // output wire [63 : 0] m_axis_iresp_tdata
.m_axis_iresp_tkeep( ), // output wire [7 : 0] m_axis_iresp_tkeep
.m_axis_iresp_tuser( ), // output wire [31 : 0] m_axis_iresp_tuser
.m_axis_treq_tvalid(treq_tvalid), // output wire m_axis_treq_tvalid
.m_axis_treq_tready(treq_tready), // input wire m_axis_treq_tready
.m_axis_treq_tlast (treq_tlast ), // output wire m_axis_treq_tlast
.m_axis_treq_tdata (treq_tdata ), // output wire [63 : 0] m_axis_treq_tdata
.m_axis_treq_tkeep (treq_tkeep ), // output wire [7 : 0] m_axis_treq_tkeep
.m_axis_treq_tuser (treq_tuser ), // output wire [31 : 0] m_axis_treq_tuser
.s_axis_tresp_tvalid(0 ), // input wire s_axis_tresp_tvalid
.s_axis_tresp_tready( ), // output wire s_axis_tresp_tready
.s_axis_tresp_tlast(0 ), // input wire s_axis_tresp_tlast
.s_axis_tresp_tdata(0 ), // input wire [63 : 0] s_axis_tresp_tdata
.s_axis_tresp_tkeep(0 ), // input wire [7 : 0] s_axis_tresp_tkeep
.s_axis_tresp_tuser(0 ), // input wire [31 : 0] s_axis_tresp_tuser
.s_axi_maintr_rst(0 ), // input wire s_axi_maintr_rst
.s_axi_maintr_awvalid(0 ), // input wire s_axi_maintr_awvalid
.s_axi_maintr_awready( ), // output wire s_axi_maintr_awready
.s_axi_maintr_awaddr(0 ), // input wire [31 : 0] s_axi_maintr_awaddr
.s_axi_maintr_wvalid(0 ), // input wire s_axi_maintr_wvalid
.s_axi_maintr_wready( ), // output wire s_axi_maintr_wready
.s_axi_maintr_wdata(0 ), // input wire [31 : 0] s_axi_maintr_wdata
.s_axi_maintr_bvalid( ), // output wire s_axi_maintr_bvalid
.s_axi_maintr_bready(0 ), // input wire s_axi_maintr_bready
.s_axi_maintr_bresp( ), // output wire [1 : 0] s_axi_maintr_bresp
.s_axi_maintr_arvalid(0 ), // input wire s_axi_maintr_arvalid
.s_axi_maintr_arready( ), // output wire s_axi_maintr_arready
.s_axi_maintr_araddr(0 ), // input wire [31 : 0] s_axi_maintr_araddr
.s_axi_maintr_rvalid( ), // output wire s_axi_maintr_rvalid
.s_axi_maintr_rready(0 ), // input wire s_axi_maintr_rready
.s_axi_maintr_rdata( ), // output wire [31 : 0] s_axi_maintr_rdata
.s_axi_maintr_rresp( ), // output wire [1 : 0] s_axi_maintr_rresp
.gt_clk_out( ), // output wire gt_clk_out
.drpclk_out( ), // output wire drpclk_out
.refclk_out( ), // output wire refclk_out
.buf_lcl_response_only_out( ), // output wire buf_lcl_response_only_out
.buf_lcl_tx_flow_control_out( ), // output wire buf_lcl_tx_flow_control_out
.idle2_selected( ), // output wire idle2_selected
.idle_selected( ), // output wire idle_selected
.buf_lcl_phy_buf_stat_out( ), // output wire [5 : 0] buf_lcl_phy_buf_stat_out
.phy_clk_out( ), // output wire phy_clk_out
.gt0_qpll_clk_out( ), // output wire gt0_qpll_clk_out
.gt0_qpll_out_refclk_out( ), // output wire gt0_qpll_out_refclk_out
.phy_rst_out( ), // output wire phy_rst_out
.sim_train_en(0), // input wire sim_train_en
.phy_mce( ), // input wire phy_mce
.phy_link_reset( ), // input wire phy_link_reset
.force_reinit( ), // input wire force_reinit
.phy_lcl_phy_next_fm_out( ), // output wire [5 : 0] phy_lcl_phy_next_fm_out
.phy_lcl_phy_last_ack_out( ), // output wire [5 : 0] phy_lcl_phy_last_ack_out
.link_initialized( ), // output wire link_initialized
.phy_lcl_phy_rewind_out( ), // output wire phy_lcl_phy_rewind_out
.phy_lcl_phy_rcvd_buf_stat_out( ), // output wire [5 : 0] phy_lcl_phy_rcvd_buf_stat_out
.phy_rcvd_mce( ), // output wire phy_rcvd_mce
.phy_rcvd_link_reset( ), // output wire phy_rcvd_link_reset
.port_error( ), // output wire port_error
.port_initialized( ), // output wire port_initialized
.clk_lock_out( ), // output wire clk_lock_out
.mode_1x( ), // output wire mode_1x
.port_timeout( ), // output wire [23 : 0] port_timeout
.srio_host( ), // output wire srio_host
.phy_lcl_master_enable_out( ), // output wire phy_lcl_master_enable_out
.phy_lcl_maint_only_out( ), // output wire phy_lcl_maint_only_out
.gtrx_disperr_or( ), // output wire gtrx_disperr_or
.gtrx_notintable_or( ), // output wire gtrx_notintable_or
.phy_debug( ), // output wire [223 : 0] phy_debug
.srio_txn0(srio_tx_n), // output wire srio_txn0
.srio_txp0(srio_tx_p), // output wire srio_txp0
.srio_rxn0(srio_rx_n), // input wire srio_rxn0
.srio_rxp0(srio_rx_p) // input wire srio_rxp0
);
ila_0 your_instance_name (
.clk(log_clk), // input wire clk
.probe0(ireq_tvalid ), // input wire [0:0] probe0
.probe1(ireq_tready ), // input wire [0:0] probe1
.probe2(ireq_tlast ), // input wire [0:0] probe2
.probe3(ireq_tdata ), // input wire [63:0] probe3
.probe4(treq_tvalid ), // input wire [0:0] probe4
.probe5(treq_tready ), // input wire [0:0] probe5
.probe6(treq_tlast ), // input wire [0:0] probe6
.probe7(treq_tdata ) // input wire [63:0] probe7
);
endmodule