IP-FIFO

IP-FIFO

1. 概述

• 先进先出队列
• 跨时钟域，数据缓冲
• 不同宽度数据匹配

2. 配置

3. 应用

verilog_to_RAM.v

module Verilog_to_FIFO
( 
	CLK_50M,RST_N,
	wrdata,rddata,wren,rden,time_cnt,usedw,full,empty
);

input CLK_50M;
input RST_N;

output reg[5:0] time_cnt;
output reg[7:0] wrdata;
output [7:0] rddata;
output wren;
output rden;
output [4:0] usedw;
output full;
output empty;


reg [5:0] time_cnt_n;
reg [7:0] wrdata_n;

always@(posedge CLK_50M or negedge RST_N)
begin
	if(!RST_N)
		time_cnt<=1'b0;
	else
		time_cnt<=time_cnt_n;
end

always@(*)
begin
	if(time_cnt==6'd63)
		time_cnt_n=1'b0;
	else
		time_cnt_n=time_cnt+1'b1;
end
//

assign wren=(time_cnt >=1'b0&&time_cnt<=5'd31)? 1'b1:1'b0;


always@(negedge CLK_50M or negedge RST_N)
begin
	if(!RST_N)
		wrdata<=1'b0;
	else
		wrdata<=wrdata_n;
end
always@(*)
begin
	if(time_cnt >=1'b0&&time_cnt<=5'd31)
		wrdata_n=time_cnt;
	else
		wrdata_n=wrdata;
end

assign rden=(time_cnt >=6'd32&&time_cnt<=6'd63)? 1'b1:1'b0;

memeory	memeory_inst (
	.clock ( CLK_50M ),
	.data ( wrdata ),
	.rdreq ( rden ),
	.wrreq ( wren ),
	.empty ( empty ),
	.full ( full ),
	.q ( rddata ),
	.usedw ( usedw )
	);
	
endmodule

verilog_to_RAM.v

`timescale 1 ps/ 1 ps
module Verilog_to_FIFO_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg CLK_50M;
reg RST_N;
// wires                                               
wire empty;
wire full;
wire [7:0]  rddata;
wire rden;
wire [5:0]  time_cnt;
wire [4:0]  usedw;
wire [7:0]  wrdata;
wire wren;

// assign statements (if any)                          
Verilog_to_FIFO i1 (
// port map - connection between master ports and signals/registers   
	.CLK_50M(CLK_50M),
	.RST_N(RST_N),
	.empty(empty),
	.full(full),
	.rddata(rddata),
	.rden(rden),
	.time_cnt(time_cnt),
	.usedw(usedw),
	.wrdata(wrdata),
	.wren(wren)
);
initial                                                
begin                                                  
	CLK_50M=1'b0;
	RST_N=1'b0;
	#10 RST_N=1'b1;
	#1000000 $stop;
end                                                    
always   #1000 CLK_50M=~CLK_50M;                                             
                                                  
endmodule

modelsim图

signaltap 图