Verilog HDL实现2~255可配置计数器

Verilog HDL实现2~255可配置计数器

源代码：
module counter_n(clk,din,rst_n,dout,count);
  input clk,rst_n;
  input[7:0]din;
  output dout;
  output[7:0]count;
  reg dout;
  reg[7:0]count;
  always@(posedge clk)
  begin
    dout<=1'b0;
    if(!rst_n)
    count<=8'b0;
    else if(count==din)
    begin count<=8'b0;dout<=1'b1; end
    else count<=count+1'b1;
  end
endmodule

测试代码
`timescale 1ns/1ns
module counter_n_tb;
  reg clk,rst_n;
  reg[7:0]din;
  wire dout;
  wire[7:0]count;
  counter_n u1(clk,din,rst_n,dout,count);
  always#10 clk=~clk;
  initial
  begin
    clk=1'b0;rst_n=1'b0;
  #10 din=8'b0000_0011;//模4计数器
  #20 rst_n=1'b1;
  #80 din=8'b0000_1000;//模9计数器
  end
endmodule