source pinlist.tcl
set file [open attribute.log w]
foreach pin $pinList {\
set vicArray [get_property [gt_pins $pin] noise_victim]
foreach_in_collection vic $vicArray {\
set input_peak [get_property $vic input_peak]
if {$input_peak > 250} {}
set vic_name
set x [get_property [get_net -of_objects $vic_name] name]
set level [get_property $vic level]
set ccap [get_property $vic level]
set vdd [get_property [get_pins $vic_name] power_rail_voltage_max]
set libs [get_libs -of_objects [get_lib_cells -of_objects [get_cells -of_objects [get_pins $vic_name]]]]
foreach_in_collection libName $libs {set library [get_property $libName hierachy_name]}
set prop_glitch [get_property $vic prop_glitch]
set_cap [format %.2f ccap]
set_annocated_glitch [get_property $vic annocated_glitch]
set reciever_peak [get_property $vic reciever_peak]
set input_peak_threshold [get_property $vic input_failure_threshold]
set reciever_peak_threshold [get_property $vic reciever_peak_threshold]
puts $file "Peak(mV) Level Total(fF) Vdd(V) Library VictimNet"
puts $file "$input_peak $level $cap $vdd $library $vic_name {$x}"
if {$reciever_peak > 0} {\
puts $file "receiver output peak :
puts $file "value recieverNet "
puts $file "receiver_peak (receiver_peak_threshold) $vic_name(CELL)"
}
if {$input_peak > 0} {\
puts $file "reciever input peak"
puts $file "value receiverNet"
puts $file "$input_peak ($input_peak_threshold) $vic_name (CELL)"
}
puts $file "\nConstraints:"
puts $file "Source Peak(mV) Offset(ps) Slew(ps) Xcap(fF) Vdd(V) Edge Status Net"
set aggs [get_property $vic attackers]
foreach_in_collection current_aggs $aggs {\
set hierarchy_name [get_property $current_agg hierarchy_name]
set noise_peak [get_property $current_agg noise_peak]
set state [get_property $current_agg state]
set slew [get_property $current_agg slew]
set edge [get_property $current_agg transition]
if {string match ~* $hierarchy_name } {\
set vdd [get_property [get_pins $vic_name] power_rail_voltage_name]
} else {\
set vdd [get_property [get_pins -of_objects [get_nets $hierarchical_name]] power_rail_voltage_max]
}
set coupling_capacitance [get_property $current_agg coupling_capacitance]
puts $file "Cpl: $noise_peak $slew $edge $vdd $coupling_capacitance $state $hierarchy_name"
if {$prop_glitch > 0} {\
puts $file "Prop: $prop_glitch"
}
}
}
}
close $file
修timing中的SI-noise问题
最新推荐文章于 2024-10-16 15:24:26 发布