AXI4-写DMA如何使用verilog实现（三）DMA例子

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已于 2022-07-07 09:02:05 修改

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分类专栏： AXI-DMA 文章标签： fpga开发

于 2022-07-05 17:18:08 首次发布

本文链接：https://blog.csdn.net/qq_44406549/article/details/125624097

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本章内容：一个DMA写的小例子

这里给一个小例子：

往0地址写入
突发长度为256突发，数据位宽为64bit
数据为0~255

//------------------------------------------------------------------------------------------------------------------------------------//
	//Ourself 
	/*
	Write Addr channel  	: 1. axi_awvalid  2. axi_awaddr   3. M_AXI_AWREADY
	Write  channel 			: 1. axi_wvalid   2. axi_wdata    3. axi_wlast     4.M_AXI_WREADY
	Write response channel	: 1. axi_bready   2. M_AXI_BVALID 3. M_AXI_BRESP
	*/     

	//--------------------------------------------------------------//
	//----------------------parameter define------------------------//
	//--------------------------------------------------------------//
	parameter ADDR_OFFSET = C_M_AXI_BURST_LEN * C_M_AXI_DATA_WIDTH >> 2;//自己写的时候可不敢这么写嗷，不能用乘法
	reg [1:0] init_valid;   
	reg [7:0] data_cnt;

	//--------------------------------------------------------------//
	//-----------------------Write Addr channel---------------------//
	//--------------------------------------------------------------//

	always @(posedge M_AXI_ACLK) begin
		init_valid <= {init_valid[0],INIT_AXI_TXN};
	end

	//axi_awvalid
	always @(posedge M_AXI_ACLK) begin
		if (M_AXI_ARESETN == 0)
			axi_awvalid <= 1'b0;
		else if(M_AXI_AWREADY == 1'b1 && axi_awvalid == 1'b1)
			axi_awvalid <= 1'b0;
		else if (init_valid == 2'b01)
			axi_awvalid <= 1'b1;
	end

	//axi_awaddr
	always @(posedge M_AXI_ACLK) begin
		if (M_AXI_ARESETN == 0) begin
			// reset
			axi_awaddr <= 32'd0;
		end
		else if (axi_awvalid == 1'b1 && M_AXI_AWREADY == 1'b1) begin
			axi_awaddr <= axi_awaddr + ADDR_OFFSET;
		end
	end
	//--------------------------------------------------------------//
	//-----------------------Write      channel---------------------//
	//--------------------------------------------------------------//
	//axi_wvalid
	always @(posedge M_AXI_ACLK) begin
		if (M_AXI_ARESETN == 0)
			axi_wvalid <= 1'b0;
		else if(axi_wlast == 1'b1 && axi_wvalid == 1'b1 && M_AXI_WREADY == 1'b1)
			axi_wvalid <= 1'b0;
		else if (axi_awvalid == 1'b1 && M_AXI_AWREADY == 1'b1)
			axi_wvalid <= 1'b1;
	end
    //data_cnt
	always @(posedge M_AXI_ACLK) begin
		if (M_AXI_ARESETN == 0)
			data_cnt <= 'd0;
		else if (axi_wvalid == 1'b1 && M_AXI_WREADY == 1'b1)
			data_cnt <= data_cnt + 1'b1;
		else if((data_cnt == C_M_AXI_BURST_LEN-1) && axi_wvalid == 1'b1 && M_AXI_WREADY == 1'b1)
			data_cnt <= 'd0;
	end

	//axi_wlast
	always @(posedge M_AXI_ACLK) begin
		if (M_AXI_ARESETN == 0)
			axi_wlast <= 1'b0;
		else if (M_AXI_WREADY == 1'b1 && axi_wvalid == 1'b1 && (data_cnt == C_M_AXI_BURST_LEN-1))
			axi_wlast <= 1'b0;
		else if (M_AXI_WREADY == 1'b1 && axi_wvalid == 1'b1 && (data_cnt == C_M_AXI_BURST_LEN-2))
			axi_wlast <= 1'b1;
	end
	//axi_wdata
	always @(*) begin
		axi_wdata <= data_cnt;
	end
	//--------------------------------------------------------------//
	//-----------------------Write response channel-----------------//
	//--------------------------------------------------------------//
	always @(posedge M_AXI_ACLK) begin
		if (M_AXI_ARESETN == 0)
			axi_bready <= 1'b0;
		else
			axi_bready <= 1'b1;
	end