FSM实现序列检测-Verilog

//FSM检测序列101
module Detect_101(
	input  clk,
	input  rst_n,
	input  data,
	output flag
    );
	 
	 parameter S0=0,S1=1,S2=2,S3=3;
	 reg [1:0] state;
	 reg [1:0] next_state;
	 
	 always @ (posedge clk or negedge rst_n)
	 begin
		if(!rst_n)
			state <= S0;
	   else
			state <= next_state; 
	 end
	 
	 always @ (*)begin
		case(state)
			S0:next_state = data ? S1:S0;
			S1:next_state = data ? S1:S2;
			S2:next_state = data ? S3:S0;
			S3:next_state = data ? S1:S2;
			default:state = S0;
		endcase
	 end
	
	always @ (posedge clk or negedge rst_n)
	begin
		if(!rst_n)
			flag <= 1'b0;
		else if(state == S3)
			flag <= 1'b1;
		else
			flag <= 1'b0;
	end

endmodule