verilog 流水线乘法，generater用法

verilog 流水线乘法，generater用法

`timescale 1ns/1ns

module multi_pipe#(
	parameter size = 4
)(
	input 						clk 		,   
	input 						rst_n		,
	input	[size-1:0]			mul_a		,
	input	[size-1:0]			mul_b		,
 
 	output	reg	[size*2-1:0]	mul_out		
);
wire	[size*2-1:0] mul[3:0];
reg	[size*2-1:0] mul_out1,mul_out2;
genvar i;
generate 
for(i=0;i<4;i=i+1)  
assign mul[i]=mul_a[i]?mul_b<<i:0;
 
endgenerate
/*
assign mul[0]=mul_a[0]?{4'b0,mul_b}:0;
assign mul[1]=mul_a[1]?{3'b0,mul_b,1'b0}:0;
assign mul[2]=mul_a[2]?{2'b0,mul_b,2'b0}:0;
assign mul[3]=mul_a[3]?{1'b0,mul_b,3'b0}:0;
*/
always@(posedge clk or negedge rst_n)
if(~rst_n) mul_out1<=0;
else mul_out1<=mul[0]+mul[1];

always@(posedge clk or negedge rst_n)
if(~rst_n) mul_out2<=0;
else mul_out2<= mul[2]+mul[3];

always@(posedge clk or negedge rst_n)
if(~rst_n) mul_out<=0;
else mul_out<=mul_out1+mul_out2;
endmodule