Verilog pcie_can_root.xdc

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本文链接：https://blog.csdn.net/qq_46621272/article/details/118249401?

PCIe TO CAN FPGA System Verilog 约束文件
复制粘贴吧 ，文件名别整错了 “pcie_can_root.xdc”
有技术问题可以联系 708907433@qq.com

#pcie_can_root.xdc
# 有技术问题可以联系 708907433@qq.com
#216
set_property PACKAGE_PIN H20		[get_ports pcie_ref_clk_p]
set_property PACKAGE_PIN G20		[get_ports pcie_ref_clk_n]
set_property PACKAGE_PIN E21		[get_ports pcie_mgt_rxn]
set_property PACKAGE_PIN F21		[get_ports pcie_mgt_rxp]
set_property PACKAGE_PIN A23		[get_ports pcie_mgt_txn]
set_property PACKAGE_PIN B23		[get_ports pcie_mgt_txp]

set_property IOSTANDARD LVCMOS33	[get_ports epc_ad[0]]
set_property IOSTANDARD LVCMOS33	[get_ports epc_ad[1]]
set_property IOSTANDARD LVCMOS33	[get_ports epc_ad[2]]
set_property IOSTANDARD LVCMOS33	[get_ports epc_ad[3]]
set_property IOSTANDARD LVCMOS33	[get_ports epc_ad[4]]
set_property IOSTANDARD LVCMOS33	[get_ports epc_ad[5]]
set_property IOSTANDARD LVCMOS33	[get_ports epc_ad[6]]
set_property IOSTANDARD LVCMOS33	[get_ports epc_ad[7]]
set_property IOSTANDARD LVCMOS33	[get_ports epc_cs_n]
set_property IOSTANDARD LVCMOS33	[get_ports epc_ads]
set_property IOSTANDARD LVCMOS33	[get_ports epc_wr_n]
set_property IOSTANDARD LVCMOS33	[get_ports epc_rd_n]
set_property IOSTANDARD LVCMOS33	[get_ports epc_int_n]
set_property IOSTANDARD LVCMOS33	[get_ports epc_rst_n]

set_property PACKAGE_PIN AA33		[get_ports epc_ad[0]]
set_property PACKAGE_PIN Y33		[get_ports epc_ad[1]]
set_property PACKAGE_PIN W34		[get_ports epc_ad[2]]
set_property PACKAGE_PIN W33		[get_ports epc_ad[3]]
set_property PACKAGE_PIN V34		[get_ports epc_ad[4]]
set_property PACKAGE_PIN V33		[get_ports epc_ad[5]]
set_property PACKAGE_PIN AB34		[get_ports epc_ad[6]]
set_property PACKAGE_PIN AC34		[get_ports epc_ad[7]]

set_property PACKAGE_PIN V31		[get_ports epc_cs_n]
set_property PACKAGE_PIN AC33		[get_ports epc_ads]
set_property PACKAGE_PIN Y32		[get_ports epc_wr_n]
set_property PACKAGE_PIN V32		[get_ports epc_rd_n]
set_property PACKAGE_PIN AA32		[get_ports epc_int_n]
set_property PACKAGE_PIN AA34		[get_ports epc_rst_n]


set_property IOSTANDARD LVCMOS33 	[get_ports clk_25mhz]
set_property PACKAGE_PIN AB31 		[get_ports clk_25mhz]

set_property IOSTANDARD LVCMOS33 	[get_ports {led_out[*]}]
set_property PACKAGE_PIN AF10 		[get_ports {led_out[0]}]
set_property PACKAGE_PIN AG10 		[get_ports {led_out[1]}]
set_property PACKAGE_PIN AG11 		[get_ports {led_out[2]}]
set_property PACKAGE_PIN AH11 		[get_ports {led_out[3]}]

create_clock -period 40.000 -name clk_25mhz 	[get_ports clk_25mhz]
create_clock -period 40.000 -name PCIE_CK_10MS	[get_pins pcie_ck_10ms_reg/Q]

# userclk1 实际上就是 axi_clk 在本设计中是 62.5MHz
set_input_delay		-clock [get_clocks userclk1] -add_delay 0.000 [get_ports {epc_ad[*]}]
set_input_delay		-clock [get_clocks userclk1] -add_delay 0.000 [get_ports epc_int_n]
set_output_delay	-clock [get_clocks userclk1] -add_delay 0.000 [get_ports {epc_ad[*]}]
set_output_delay	-clock [get_clocks userclk1] -add_delay 0.000 [get_ports epc_cs_n]
set_output_delay	-clock [get_clocks userclk1] -add_delay 0.000 [get_ports epc_ads]
set_output_delay	-clock [get_clocks userclk1] -add_delay 0.000 [get_ports epc_wr_n]
set_output_delay	-clock [get_clocks userclk1] -add_delay 0.000 [get_ports epc_rd_n]
set_output_delay	-clock [get_clocks userclk1] -add_delay 0.000 [get_ports epc_rst_n]
set_output_delay	-clock [get_clocks userclk1] -add_delay 0.000 [get_ports {led_out[*]}]

####################################################################################################
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design]
set_property CONFIG_MODE SPIx4 [current_design]

####################################################################################################
##												end
####################################################################################################

连接：采用 FPGA 实现 ＜PCIe to CAN＞ 网卡的设计 https://blog.csdn.net/qq_46621272/article/details/118242161?