FIR 高级应用 FIR Reload 的使用

本文链接：https://blog.csdn.net/qq_46621272/article/details/125348908

FIR 高级应用 FIR Reload 的使用

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前言

这是 XILINX FIR IP 详解、Verilog 源码、Vivado 工程 这篇文章的实验部分，FIR IP Reload 在线编程。

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1. reload_fir_testbench.v verilog 代码

///////////////////////////////////////////////////////////////////////

`timescale 1ns / 100ps
//reload_fir_testbench.v
module reload_fir_testbench;

reg			rst_n;
reg			clk;
reg			clk_10khz;

parameter CLK_PERIOD		= 1000;		//1MHz 采样频率

parameter CLK_10K			= CLK_PERIOD * 100;

initial	begin
	rst_n	= 0;
	#(20 * CLK_PERIOD)
	rst_n	= 1;
	#(6000 * CLK_PERIOD)
	$stop;
end

initial
begin
	clk			= 0;
	clk_10khz	= 0;
end

always	clk			= #(CLK_PERIOD/2.0) ~clk;
always	clk_10khz	= #(CLK_10K/2.0) ~clk_10khz;


	wire 	signed[15:0]	s_tdata;
	wire					s_tvalid;
	wire					s_tready;

	wire 	signed[15:0]	m_tdata;
	wire					m_tvalid;
	wire					m_tready;
	

	assign	s_tdata  = clk_10khz == 0 ? -10000:10000;
	assign	s_tvalid = s_tready;
	assign	m_tready = 1;

	reload_fir am_fir_u1
	(
		.rst_n					(rst_n),					// input wire aresetn
		.clk					(clk),						// input wire aclk
		.s_axis_data_tvalid		(s_tvalid),					// input wire s_axis_data_tvalid
		.s_axis_data_tready		(s_tready),					// output wire s_axis_data_tready
		.s_axis_data_tdata		(s_tdata),					// input wire [15 : 0] s_axis_data_tdata
		.m_axis_data_tvalid		(m_tvalid),					// output wire m_axis_data_tvalid
		.m_axis_data_tready		(m_tready),					// input wire m_axis_data_tready
		.m_axis_data_tdata		(m_tdata)					// output wire [15 : 0] m_axis_data_tdata
	);

endmodule

2. reload_fir.v verilog 代码

//reload_fir.v
module	reload_fir
(
	input					rst_n,
	input					clk,
	input					s_axis_data_tvalid,
	output					s_axis_data_tready,
	input	signed[15:0]	s_axis_data_tdata,
	output					m_axis_data_tvalid,
	input					m_axis_data_tready,
	output	signed[15:0]	m_axis_data_tdata
);

	wire				fir_tlast_missing;
	wire				fir_tlast_unexpected;
	wire	[39:0]		m_axis_data_tdata_i;

	wire[15:0]		fir_reload_dat[3:0][127:0];
	reg	[15:0]		fir_dat0[127:0];
	reg	[15:0]		fir_dat1[127:0];
	reg	[15:0]		fir_dat2[127:0];
	reg	[15:0]		fir_dat3[127:0];


	wire [07:0]	fir_s_cfg_tdata;
	wire		fir_s_cfg_tvalid;
	wire		fir_s_cfg_tready;

	reg [15:0]	fir_s_reload_tdata;
	reg			fir_s_reload_tvalid;
	wire		fir_s_reload_tready;
	reg			fir_s_reload_tlast;
    
    genvar  m;

    for(m=0;m<128;m=m+1)
    begin:for_mx
        assign	fir_reload_dat[0][m]	= fir_dat0[m];
        assign	fir_reload_dat[1][m]	= fir_dat1[m];
        assign	fir_reload_dat[2][m]	= fir_dat2[m];
        assign	fir_reload_dat[3][m]	= fir_dat3[m];
    end

	initial
	begin
		$readmemh("../../../../../reload_bandpass_10k_30k_30k_50k_1m.txt",	fir_dat0);
		$readmemh("../../../../../reload_bandpass_30k_50k_50k_70k_1m.txt",	fir_dat1);
		$readmemh("../../../../../reload_bandpass_50k_70k_70k_90k_1m.txt",	fir_dat2);
		$readmemh("../../../../../reload_bandpass_70k_90k_90k_110k_1m.txt",	fir_dat3);
	end
		
	parameter	NUMBER_COE_SIZE = 128;	//64;
	parameter	NUMBER_COE_SETS = 2;	//
	
	reg	[15:0]	reload_cnt=16'hffff;
	reg	[15:0]	cfg_cnt=0;
	wire		reload_en;
	reg	[1:0]	reload_sn=0;
	reg[15:0]	fir_cntx=0;
	reg[15:0]	psel=0;
	reg[15:0]	w_psel=1;

	assign	fir_s_cfg_tdata		= psel;
	assign	fir_s_cfg_tvalid	= cfg_cnt == 0    ? 1:0;
	assign	reload_en			= fir_cntx[9:0] == 0 && fir_cntx != 0  ? 1:0;
	
	always @(posedge clk)
	begin
		if(rst_n == 0 )
		begin
			fir_s_reload_tdata	<= 0;
			fir_s_reload_tvalid	<= 0;
			fir_s_reload_tlast	<= 0;
		end
		else if(fir_s_reload_tready == 1)
		begin
			if(NUMBER_COE_SETS == 1)
			begin
			
				if(reload_cnt == NUMBER_COE_SIZE-1)
					fir_s_reload_tlast	<= 1;
				else
					fir_s_reload_tlast	<= 0;
			
				if(reload_cnt < NUMBER_COE_SIZE)
				begin
					fir_s_reload_tdata	<= fir_reload_dat[reload_sn][reload_cnt];
					fir_s_reload_tvalid	<= 1;
				end	
				else
				begin
					fir_s_reload_tdata	<= 0;
					fir_s_reload_tvalid	<= 0;
				end	
			end
			else
			begin
				if(reload_cnt == NUMBER_COE_SIZE)
					fir_s_reload_tlast	<= 1;
				else
					fir_s_reload_tlast	<= 0;

				if(reload_cnt<NUMBER_COE_SIZE+1)
				begin
					fir_s_reload_tvalid	<= 1;
					if(reload_cnt == 0)
						fir_s_reload_tdata	<= w_psel;
					else
						fir_s_reload_tdata	<= fir_reload_dat[reload_sn][reload_cnt-1];
				end	
				else
				begin
					fir_s_reload_tdata	<= 0;
					fir_s_reload_tvalid	<= 0;
				end
			end
		end
	end

	always @(posedge clk)
	begin
		if(rst_n == 0 )
		begin
			fir_cntx	<= 0;
		end
		else if(fir_s_reload_tready == 1 && fir_s_cfg_tready == 1)
		begin
			fir_cntx	<= fir_cntx + 1;
		end
	end

	always @(posedge clk)
	begin
		if(rst_n == 0 )
		begin
			reload_sn	<= 0;
			psel		<= 0;
		end
		else if(fir_s_reload_tlast == 1 && fir_s_reload_tready == 1)
		begin
			reload_sn	<= reload_sn + 1;
			psel		<= 1;
		end
	end


	always @(posedge clk)
	begin
		if(rst_n == 0 )
		begin
			reload_cnt		<= 16'hffff;
		end
		else if(reload_en == 1)
		begin
			reload_cnt		<= 0;
		end
		else if(fir_s_reload_tready == 1)
		begin
			if(reload_cnt != 16'hffff)
				reload_cnt	<= reload_cnt + 1;
		end
	end

	always @(posedge clk)
	begin
		if(rst_n == 0 ||(fir_s_reload_tlast == 1 && fir_s_reload_tready == 1))
		begin
			cfg_cnt		<= 0;
		end
		else if(fir_s_cfg_tready == 1)
		begin
			if(fir_s_cfg_tvalid == 1 || cfg_cnt != 16'hffff)
				cfg_cnt	<= cfg_cnt + 1;
		end
	end

	assign	m_axis_data_tdata = m_axis_data_tdata_i >> 18;

	reload_fir_256x2 am_fir_u1
	(
		.aresetn				(rst_n),					// input wire aresetn
		.aclk					(clk),						// input wire aclk
		.s_axis_config_tvalid	(fir_s_cfg_tvalid),			// input wire s_axis_config_tvalid
		.s_axis_config_tready	(fir_s_cfg_tready),			// output wire s_axis_config_tready
		.s_axis_config_tdata	(fir_s_cfg_tdata),			// input wire [7 : 0] s_axis_config_tdata
		.s_axis_reload_tvalid	(fir_s_reload_tvalid),		// input wire s_axis_reload_tvalid
		.s_axis_reload_tready	(fir_s_reload_tready),		// output wire s_axis_reload_tready
		.s_axis_reload_tlast	(fir_s_reload_tlast),		// input wire s_axis_reload_tlast
		.s_axis_reload_tdata	(fir_s_reload_tdata),		// input wire [15 : 0] s_axis_reload_tdata
		.s_axis_data_tvalid		(s_axis_data_tvalid),		// input wire s_axis_data_tvalid
		.s_axis_data_tready		(s_axis_data_tready),		// output wire s_axis_data_tready
		.s_axis_data_tdata		(s_axis_data_tdata),		// input wire [15 : 0] s_axis_data_tdata
		.m_axis_data_tvalid		(m_axis_data_tvalid),		// output wire m_axis_data_tvalid
		.m_axis_data_tready		(m_axis_data_tready),		// input wire m_axis_data_tready
		.m_axis_data_tdata		(m_axis_data_tdata_i),		// output wire [39 : 0] m_axis_data_tdata
		.event_s_reload_tlast_missing	(fir_tlast_missing),	// output wire event_s_reload_tlast_missing
		.event_s_reload_tlast_unexpected(fir_tlast_unexpected)	// output wire event_s_reload_tlast_unexpected
	);

endmodule

3. 仿真时序波形图

4. FIR IP 设置

5. FIR IP 系数文件

a. reload_lowpass_10k_30k_1m.coe 采样频率 1MHz 10KHz 低通滤波器 COE 文件

; XILINX CORE Generator(tm)Distributed Arithmetic FIR filter coefficient (.COE) File
; Generated by MATLAB(R) 9.7 and DSP System Toolbox 9.9.
; Generated on: 16-Jun-2022 16:20:42
Radix = 16; 
Coefficient_Width = 16; 
CoefData = 
fd36,fed1,fe98,fe5f,fe27,fdf3,fdc4,fd9c,fd80,fd72,fd74,fd8a,fdb8,fe00,fe67,feed,
ff99,006b,0166,028d,03e0,0561,0711,08ef,0afb,0d34,0f98,1224,14d5,17a7,1a94,1d9a,
20b0,23d2,26f9,2a1d,2d37,3041,3333,3604,38af,3b2d,3d75,3f84,4152,42db,441b,450e,
45b1,4603,4603,45b1,450e,441b,42db,4152,3f84,3d75,3b2d,38af,3604,3333,3041,2d37,
2a1d,26f9,23d2,20b0,1d9a,1a94,17a7,14d5,1224,0f98,0d34,0afb,08ef,0711,0561,03e0,
028d,0166,006b,ff99,feed,fe67,fe00,fdb8,fd8a,fd74,fd72,fd80,fd9c,fdc4,fdf3,fe27,
fe5f,fe98,fed1,fd36;

b. reload_lowpass_10k_30k_1m.coe 采样频率 1MHz 10KHz 低通滤波器 MATLAB 设置

c. reload_highass_10k_30k_1m.coe 采样频率 1MHz 10KHz 高通滤波器 COE 文件

; XILINX CORE Generator(tm)Distributed Arithmetic FIR filter coefficient (.COE) File
; Generated by MATLAB(R) 9.7 and DSP System Toolbox 9.9.
; Generated on: 16-Jun-2022 16:23:18
Radix = 16; 
Coefficient_Width = 16; 
CoefData = 
0151,fec6,ff2f,ff70,ff98,ffb3,ffc6,ffd5,ffe3,fff0,ffff,0010,0021,0034,0049,005e,
0073,0088,009c,00ae,00bf,00cc,00d6,00dc,00dd,00d8,00cd,00bc,00a4,0084,005e,0030,
fffb,ffbf,ff7d,ff34,fee6,fe94,fe3d,fde4,fd89,fd2d,fcd1,fc77,fc21,fbce,fb80,fb38,
faf8,fac0,fa90,fa6b,fa50,fa40,7a3b,fa40,fa50,fa6b,fa90,fac0,faf8,fb38,fb80,fbce,
fc21,fc77,fcd1,fd2d,fd89,fde4,fe3d,fe94,fee6,ff34,ff7d,ffbf,fffb,0030,005e,0084,
00a4,00bc,00cd,00d8,00dd,00dc,00d6,00cc,00bf,00ae,009c,0088,0073,005e,0049,0034,
0021,0010,ffff,fff0,ffe3,ffd5,ffc6,ffb3,ff98,ff70,ff2f,fec6,0151;

d. reload_highass_10k_30k_1m.coe 采样频率 1MHz 10KHz 高通滤波器 MATLAB 设置

e. 上面俩文件合并成一个文件 reload_fir_128x2.coe

; XILINX CORE Generator(tm)Distributed Arithmetic FIR filter coefficient (.COE) File
; Generated by MATLAB(R) 9.7 and DSP System Toolbox 9.9.
; Generated on: 16-Jun-2022 16:20:42
Radix = 16; 
Coefficient_Width = 16; 
CoefData = 
fd36,fed1,fe98,fe5f,fe27,fdf3,fdc4,fd9c,fd80,fd72,fd74,fd8a,fdb8,fe00,fe67,feed,
ff99,006b,0166,028d,03e0,0561,0711,08ef,0afb,0d34,0f98,1224,14d5,17a7,1a94,1d9a,
20b0,23d2,26f9,2a1d,2d37,3041,3333,3604,38af,3b2d,3d75,3f84,4152,42db,441b,450e,
45b1,4603,4603,45b1,450e,441b,42db,4152,3f84,3d75,3b2d,38af,3604,3333,3041,2d37,
2a1d,26f9,23d2,20b0,1d9a,1a94,17a7,14d5,1224,0f98,0d34,0afb,08ef,0711,0561,03e0,
028d,0166,006b,ff99,feed,fe67,fe00,fdb8,fd8a,fd74,fd72,fd80,fd9c,fdc4,fdf3,fe27,
fe5f,fe98,fed1,fd36,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,
0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,
0151,fec6,ff2f,ff70,ff98,ffb3,ffc6,ffd5,ffe3,fff0,ffff,0010,0021,0034,0049,005e,
0073,0088,009c,00ae,00bf,00cc,00d6,00dc,00dd,00d8,00cd,00bc,00a4,0084,005e,0030,
fffb,ffbf,ff7d,ff34,fee6,fe94,fe3d,fde4,fd89,fd2d,fcd1,fc77,fc21,fbce,fb80,fb38,
faf8,fac0,fa90,fa6b,fa50,fa40,7a3b,fa40,fa50,fa6b,fa90,fac0,faf8,fb38,fb80,fbce,
fc21,fc77,fcd1,fd2d,fd89,fde4,fe3d,fe94,fee6,ff34,ff7d,ffbf,fffb,0030,005e,0084,
00a4,00bc,00cd,00d8,00dd,00dc,00d6,00cc,00bf,00ae,009c,0088,0073,005e,0049,0034,
0021,0010,ffff,fff0,ffe3,ffd5,ffc6,ffb3,ff98,ff70,ff2f,fec6,0151,0000,0000,0000,
0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000,0000;

6. Reload 系数文件

a. reload_bandpass_10k_30k_30k_50k_1m.coe 采样频率 1MHz 30KHz 带通滤波器MATLAB 设置

b. reload_bandpass_10k_30k_30k_50k_1m.coe 采样频率 1MHz 30KHz 带通滤波器 COE 文件

; XILINX CORE Generator(tm)Distributed Arithmetic FIR filter coefficient (.COE) File
; Generated by MATLAB(R) 9.7 and DSP System Toolbox 9.9.
; Generated on: 16-Jun-2022 16:17:22
Radix = 16; 
Coefficient_Width = 16; 
CoefData = 
f600,fae0,fa07,f978,f952,f9b6,fac0,fc84,ff0b,0255,0654,0aeb,0fed,151d,1a3a,1eeb,
22e0,25bd,2730,26f0,24c1,207f,1a1d,11ab,0756,fb6a,ee52,e091,d2bc,c57b,b976,af57,
a7bb,a327,a206,a49e,ab0a,b537,c2e4,d3a2,e6da,fbd0,11ae,278a,3c79,4f90,5ffa,6cfb,
75fe,7a9a,7a9a,75fe,6cfb,5ffa,4f90,3c79,278a,11ae,fbd0,e6da,d3a2,c2e4,b537,ab0a,
a49e,a206,a327,a7bb,af57,b976,c57b,d2bc,e091,ee52,fb6a,0756,11ab,1a1d,207f,24c1,
26f0,2730,25bd,22e0,1eeb,1a3a,151d,0fed,0aeb,0654,0255,ff0b,fc84,fac0,f9b6,f952,
f978,fa07,fae0,f600;

d. reload_bandpass_10k_30k_30k_50k_1m.txt 编辑过的 Reload 系数文件

f600 fae0 fa07 f978 f952 f9b6 fac0 fc84 ff0b 0255 0654 0aeb 0fed 151d 1a3a 1eeb
22e0 25bd 2730 26f0 24c1 207f 1a1d 11ab 0756 fb6a ee52 e091 d2bc c57b b976 af57
a7bb a327 a206 a49e ab0a b537 c2e4 d3a2 e6da fbd0 11ae 278a 3c79 4f90 5ffa 6cfb
75fe 7a9a 7a9a 75fe 6cfb 5ffa 4f90 3c79 278a 11ae fbd0 e6da d3a2 c2e4 b537 ab0a
a49e a206 a327 a7bb af57 b976 c57b d2bc e091 ee52 fb6a 0756 11ab 1a1d 207f 24c1
26f0 2730 25bd 22e0 1eeb 1a3a 151d 0fed 0aeb 0654 0255 ff0b fc84 fac0 f9b6 f952
f978 fa07 fae0 f600 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 

e. reload_bandpass_30k_50k_50k_70k_1m.coe 采样频率 1MHz 50KHz 带通滤波器 MATLAB 设置

f. reload_bandpass_30k_50k_50k_70k_1m.coe 采样频率 1MHz 50KHz 带通滤波器 COE 文件

; XILINX CORE Generator(tm)Distributed Arithmetic FIR filter coefficient (.COE) File
; Generated by MATLAB(R) 9.7 and DSP System Toolbox 9.9.
; Generated on: 16-Jun-2022 16:18:09
Radix = 16; 
Coefficient_Width = 16; 
CoefData = 
f6c3,fba8,fbb5,fcad,feb1,01bc,059e,09f9,0e42,11d2,13f9,1415,11ac,0c85,04c3,fadd,
efb9,e47f,da91,d35b,d026,d1eb,d923,e5af,f6c4,0af2,2044,346c,4502,4fd2,531d,4ddf,
3ff9,2a48,0e9a,ef8b,d041,b41a,9e46,916b,8f4e,9899,acbb,c9ec,ed5c,1379,3855,5811,
6f52,7b9a,7b9a,6f52,5811,3855,1379,ed5c,c9ec,acbb,9899,8f4e,916b,9e46,b41a,d041,
ef8b,0e9a,2a48,3ff9,4ddf,531d,4fd2,4502,346c,2044,0af2,f6c4,e5af,d923,d1eb,d026,
d35b,da91,e47f,efb9,fadd,04c3,0c85,11ac,1415,13f9,11d2,0e42,09f9,059e,01bc,feb1,
fcad,fbb5,fba8,f6c3;

g. reload_bandpass_30k_50k_50k_70k_1m.txt 编辑过的 Reload 系数文件

f6c3 fba8 fbb5 fcad feb1 01bc 059e 09f9 0e42 11d2 13f9 1415 11ac 0c85 04c3 fadd
efb9 e47f da91 d35b d026 d1eb d923 e5af f6c4 0af2 2044 346c 4502 4fd2 531d 4ddf
3ff9 2a48 0e9a ef8b d041 b41a 9e46 916b 8f4e 9899 acbb c9ec ed5c 1379 3855 5811
6f52 7b9a 7b9a 6f52 5811 3855 1379 ed5c c9ec acbb 9899 8f4e 916b 9e46 b41a d041
ef8b 0e9a 2a48 3ff9 4ddf 531d 4fd2 4502 346c 2044 0af2 f6c4 e5af d923 d1eb d026
d35b da91 e47f efb9 fadd 04c3 0c85 11ac 1415 13f9 11d2 0e42 09f9 059e 01bc feb1
fcad fbb5 fba8 f6c3 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 

e. reload_bandpass_50k_70k_70k_90k_1m.coe 采样频率 1MHz 70KHz 带通滤波器 MATLAB 设置

h. reload_bandpass_50k_70k_70k_90k_1m.coe 采样频率 1MHz 70KHz 带通滤波器 COE 文件

; XILINX CORE Generator(tm)Distributed Arithmetic FIR filter coefficient (.COE) File
; Generated by MATLAB(R) 9.7 and DSP System Toolbox 9.9.
; Generated on: 16-Jun-2022 16:18:47
Radix = 16; 
Coefficient_Width = 16; 
CoefData = 
f756,fcaf,fdeb,009c,0476,08c1,0c70,0e54,0d65,0916,0198,f7f2,edf0,e5d8,e1f4,e3fa,
ec96,fb03,0d08,1f3a,2da0,3483,3155,2367,0c54,efe7,d386,bd2b,b228,b5e7,c901,e8e0,
1000,36ee,55b0,6575,6216,4b20,2424,f42a,c467,9e67,8a1a,8c1a,a4a5,cf6d,045f,393a,
639e,7b26,7b26,639e,393a,045f,cf6d,a4a5,8c1a,8a1a,9e67,c467,f42a,2424,4b20,6216,
6575,55b0,36ee,1000,e8e0,c901,b5e7,b228,bd2b,d386,efe7,0c54,2367,3155,3483,2da0,
1f3a,0d08,fb03,ec96,e3fa,e1f4,e5d8,edf0,f7f2,0198,0916,0d65,0e54,0c70,08c1,0476,
009c,fdeb,fcaf,f756;

i. reload_bandpass_50k_70k_70k_90k_1m.txt 编辑过的 Reload 系数文件

f756 fcaf fdeb 009c 0476 08c1 0c70 0e54 0d65 0916 0198 f7f2 edf0 e5d8 e1f4 e3fa
ec96 fb03 0d08 1f3a 2da0 3483 3155 2367 0c54 efe7 d386 bd2b b228 b5e7 c901 e8e0
1000 36ee 55b0 6575 6216 4b20 2424 f42a c467 9e67 8a1a 8c1a a4a5 cf6d 045f 393a
639e 7b26 7b26 639e 393a 045f cf6d a4a5 8c1a 8a1a 9e67 c467 f42a 2424 4b20 6216
6575 55b0 36ee 1000 e8e0 c901 b5e7 b228 bd2b d386 efe7 0c54 2367 3155 3483 2da0
1f3a 0d08 fb03 ec96 e3fa e1f4 e5d8 edf0 f7f2 0198 0916 0d65 0e54 0c70 08c1 0476
009c fdeb fcaf f756 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 

g. reload_bandpass_70k_90k_90k_110k_1m.coe 采样频率 1MHz 90KHz 带通滤波器 MATLAB 设置

j. reload_bandpass_70k_90k_90k_110k_1m.coe 采样频率 1MHz 90KHz 带通滤波器 COE 文件

; XILINX CORE Generator(tm)Distributed Arithmetic FIR filter coefficient (.COE) File
; Generated by MATLAB(R) 9.7 and DSP System Toolbox 9.9.
; Generated on: 16-Jun-2022 16:19:25
Radix = 16; 
Coefficient_Width = 16; 
CoefData = 
f7cb,fdd7,0054,0461,08b6,0b81,0b07,0663,fe28,f47e,ecb2,ea27,ef04,fb21,0b98,1b4c,
2475,2297,1474,fcf9,e2e2,ceda,c8a9,d451,f024,14a7,367e,49f1,46f5,2c4f,00a7,d0ff,
acc7,a0da,b2ec,df1e,18aa,4d94,6c6a,6a10,45c4,09d6,c8ad,9707,853c,99c1,ced2,1414,
53bf,799e,799e,53bf,1414,ced2,99c1,853c,9707,c8ad,09d6,45c4,6a10,6c6a,4d94,18aa,
df1e,b2ec,a0da,acc7,d0ff,00a7,2c4f,46f5,49f1,367e,14a7,f024,d451,c8a9,ceda,e2e2,
fcf9,1474,2297,2475,1b4c,0b98,fb21,ef04,ea27,ecb2,f47e,fe28,0663,0b07,0b81,08b6,
0461,0054,fdd7,f7cb;

k. reload_bandpass_70k_90k_90k_110k_1m.txt 编辑过的 Reload 系数文件

f7cb fdd7 0054 0461 08b6 0b81 0b07 0663 fe28 f47e ecb2 ea27 ef04 fb21 0b98 1b4c
2475 2297 1474 fcf9 e2e2 ceda c8a9 d451 f024 14a7 367e 49f1 46f5 2c4f 00a7 d0ff
acc7 a0da b2ec df1e 18aa 4d94 6c6a 6a10 45c4 09d6 c8ad 9707 853c 99c1 ced2 1414
53bf 799e 799e 53bf 1414 ced2 99c1 853c 9707 c8ad 09d6 45c4 6a10 6c6a 4d94 18aa
df1e b2ec a0da acc7 d0ff 00a7 2c4f 46f5 49f1 367e 14a7 f024 d451 c8a9 ceda e2e2
fcf9 1474 2297 2475 1b4c 0b98 fb21 ef04 ea27 ecb2 f47e fe28 0663 0b07 0b81 08b6
0461 0054 fdd7 f7cb 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 

7. 相关 vivado 工程、IP 设置等详细文档连接，采用 Xilinx vivado 2017.4 版本

• XILINX FIR IP 详解、Verilog 源码、Vivado 工程

• FIR 基础应用 - AM 调幅波调制解调(FIR 低通滤波)详细介绍

• FIR 基础应用 - FM 调频波调制解调(FIR 低通滤波) 详细介绍

• FIR 中级应用 - AM 调幅波调制解调(FIR + FIFO)详细介绍

• FIR 高级应用 - AM 调幅波调制解调(FIR 低通滤波+重采样，FIR 高阶系数，FIR+FIFO ) 详细介绍

• FIR 高级应用 - 多通道实验 (四个通道用一个 FIR IP，每通道用不同的系数) 详细介绍

• FIR 高级应用 FIR Reload的使用) 详细介绍

• AM 调幅波调制解调(FIR 低通滤波) vivado 工程文件下载

• FM 调频波调制解调(FIR 低通滤波) Vivado 工程文件下载

• AM 调幅波调制解调(FIR + FIFO) Vivado 工程文件下载

• AM 调幅波调制解调(FIR 低通滤波+重采样，FIR 高阶系数，FIR+FIFO ) Vivado 工程文件下载

• FIR 高级应用 - 多通道实验 Vivado 工程文件下载

• FIR 高级应用 FIR Reload 的使用 vivado 工程文件下载