基于FPGA的序列检测

工作总结

检测1010101序列

详细设计

//程序代码

module xljc_1(clk,rst,din,dout

    );

input clk,rst,din;

output reg dout;

reg[2:0]state;

parameter S1=4'b0001,S2=4'b0011,S3=4'b0010,S4=4'b0110,S5=4'b0111,S6=4'b0101,S7=4'b0100;

always@(posedge clk or negedge rst)

begin if(!rst) state<=S1;

   else case(state)

    S1: begin if(din) begin state<=S2; dout=1'b0; end

              else begin state<=S1; dout=1'b0; end end

 S2: begin if(din) begin state<=S2; dout=1'b0; end

              else begin state<=S3; dout=1'b0; end end

 S3: begin if(din) begin state<=S4; dout=1'b0; end

              else begin state<=S1; dout=1'b0; end end

 S4: begin if(din) begin state<=S2; dout=1'b0; end

              else begin state<=S5; dout=1'b0; end end

 S5: begin if(din) begin state<=S6; dout=1'b0; end

              else begin state<=S1; dout=1'b0; end end

 S6: begin if(din) begin state<=S2; dout=1'b0; end

              else begin state<=S7; dout=1'b0; end end

 S7: begin if(din) begin state<=S6; dout=1'b1; end

              else begin state<=S1; dout=1'b0; end end

default:  begin

           state<=S1;

  dout=1'b0;

 end

   endcase

end

endmodule

总体验证方案

//仿真

module sc;

// Inputs

reg clk;

reg rst;

reg din;

// Outputs

wire dout;

// Instantiate the Unit Under Test (UUT)

xljc_1 uut (

.clk(clk),

.rst(rst),

.din(din),

.dout(dout)

);

   always #10 clk = ~clk;

initial begin

// Initialize Inputs

clk = 0;

rst = 0;

din = 0;

// Wait 100 ns for global reset to finish

#100;

      rst = 1;

din = 1;

#20;

din = 0;

#20;

din = 1;

#20;

din = 0;

#20;

din = 1;

#20;

din = 0;

#20;

din = 1;

#20;

din = 0;

#20;

din = 1;

#20;

din = 0;

#20;

din = 1;

#20;

din = 0;

// Add stimulus here

end

endmodule