Verilog状态机

//红绿灯状态机的设计

module trafficlight1(clock,reset,red,yellow,green);
input clock,seset;
output red,yellow,green;
reg red,yellow,green;
reg[1:0] current_state,next_state;
parameter red_state = 2'b00;
		 yellow_state = 2'b01,
		 green_state = 2'b10,
		 delay_r2y = 4'd8,
		 delay_y2g = 4'd3,
		 delay_g2r = 4'd11;
//第一段，用于把下一状态赋值给当前状态
always@(posedge clock or posedge reset)
begin 
if(reset)
current_state <= red_state;
else 
current_state <= next_state;
end
//第二段always，用于根据当前状态判断下一状态，并产生输出
always@(current_state)
begin 
case(current_state)
red state:begin
		red = 1;
		yellow=0;
		green = 0;
		repeat(delay_r2y)@(posedge clock);
		next_state = yellow_state;
		end
yellow state:begin
		red = 0;
		yellow=1;
		green = 0;
		repeat(delay_y2g)@(posedge clock);
		next_state = green_state;
		end	
green state:begin
		red = 0;
		yellow=0;
		green = 1;
		repeat(delay_g2r)@(posedge clock);
		next_state = red_state;
		end		
default:begin
		red = 1;
		yellow=0;
		green = 0;
		next_state = red_state;
		end	
endcase
end
endmodule