module top_module (
input clk,
input [2:0] y,
input x,
output Y0,
output z
); reg [2:0]next_state;
parameter s0 = 3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100;
always@(*)begin
case(y[2:0])
s0:next_state = x?s1:s0;
s1:next_state = x?s4:s1;
s2:next_state = x?s1:s2;
s3:next_state = x?s2:s1;
s4:next_state = x?s4:s3;
endcase
end
assign z = (y[2:0] ==s3|y[2:0] ==s4);
assign Y0 = next_state[0];
endmodule
Verilog 刷题 - Exams/2014 q3c
最新推荐文章于 2024-06-11 09:46:02 发布