牛客网verilog VL29 信号发生器

 题意不清，按照测试调出来的，意义不大，也就1个半小时，相当奔溃。

`timescale 1ns/1ns
module signal_generator(
	input clk,
	input rst_n,
	input [1:0] wave_choise,
	output reg [4:0]wave
	);
reg [4:0]cont1;
reg [4:0]cont2;
reg flag;
	always@(negedge rst_n)begin
		wave <= 0;
		cont1 <= 0;
		cont2 <= 0;
		flag <= 0;
	end

	always@(posedge clk)begin
		case(wave_choise)
			0:begin
				cont2<=0;
				cont1 <= (cont1 < 5'd19) ? (cont1+1):0;
				wave = (cont1 < 10) ? 0: 20;
			end
			1:begin
				cont1<=0;
				cont2 <= (cont2 < 5'd20) ? (cont2+1):0;
				wave = cont2;				
			end
			2:begin
				cont1<=0;
				if(cont2>1)begin
					cont2 =cont2-1;
					wave = cont2-1;
				end
				else begin
					if(wave == 0)begin
						flag = 1;
					end
					else if(wave == 20)begin
						flag = 0 ;
					end
					else begin
						flag <= flag;
					end
					wave = (flag)? wave+1:wave-1;
				end
			end
		endcase
	end
endmodule