Clock frequency recovery from timestamp

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Clock frequency recovery from timestamp
Q1:

I want to synchronize a slave board to a master board. Master is sending time stamps over link.

On the slave side this time stamp is compared to local counter and the clock “adjusted”(similar to ethernet avb approach).

In some app notes there are using external vcxo to correct the clock drift.

Are there any reference design for a FPGA based all digital pll available? The clock frequency which needs to be recovered is roughly 5MHz.

Any help is appreciated.

A1:
I’ve used the PICXO PLL design in XAPP589 as a general purpose PLL (the version without a transceiver). I would not recommend it, because it’s encrypted and can’t be simulated. This leaves 3 other possibilities.

1. Write some code to implement a 2nd (or higher) order DPLL that uses the MMCM phase shifter input as a frequency modulated oscillator. I did this using an accumulator to generate positive and negative phase shifts on an accumulator overflow/underflow condition. This allowed the MMCM to track an external clock. In your case, the received time stamp is used to generate a late/early condition that is used to emulate the phase comparator of the DPLL.

2. The gigabit tranceivers (series 7 and newer) have TX phase modulation capability, with somewhat smaller phase steps than the MMCM phase shifters. If you have a spare, it can be used as a VCO with 1000 ppm pull range, just like in XAPP589.

3. Write an all digital DSP circuit that filters the timestamp updates, and directly modulate the updates of your local clock (local timestamp counter). This is probably the best solution, since you can use as many bits of precision as you need in your estimates, filtering, and finally accumulation. A pair of DSP48’s can be used to implement a 96 bit accumulator at quite a high clock rate. With enough bits of precision, your local drift will be essentially the short term stability of your slave board oscillator.

Q2:
Thank you. Can you elaborate point three in more details?

Time_stamp_comparison_out -> filter -> DCO(dsp based accumulator) -> output_clock

I am worried about timing since output_clock is generated from logic.

A2:
you need to be more precise in your definition of “local clock”. Is this a physical clock signal at 5 MHz (or some other frequency) ? Or is the “local clock” just a counter that is a timestamp? Or is it a clock enable signal generated by a local oscillator, where the enable signal is frequency locked to the remote master?

If you need to synthesize a local clock signal at some frequency locked to the remote master, then the MMCM approach is the way to go. If it’s a timestamp counter, then all digital dsp is the path. An enable signal that’s frequency locked is all digital too.

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