Verilog刷题笔记7

题目：

Connecting Signals to Module Ports There are two commonly-used methods to connect a wire to a port: by position or by name.
By position The syntax to connect wires to ports by position should be familiar, as it uses a C-like syntax. When instantiating a module, ports are connected left to right according to the module’s declaration. For example:
mod_a instance1 ( wa, wb, wc );
This instantiates a module of type and gives it an instance name of “instance1”, then connects signal (outside the new module) to the first port () of the new module, to the second port (), and to the third port (). One drawback of this syntax is that if the module’s port list changes, all instantiations of the module will also need to be found and changed to match the new module. mod_awain1wbin2wcout
By name Connecting signals to a module’s ports by name allows wires toremain correctly connected even if the port list changes. This syntax is more verbose, however.
mod_a instance2 ( .out(wc), .in1(wa), .in2(wb) );
The above line instantiates a module of type named “instance2”, then connects signal (outside the module) to the port named , to the port named , and to the port named . Notice how the ordering of ports is irrelevant here because the connection will be made to the correct name, regardless of its position in the sub-module’s port list. Also notice the period immediately preceding the port name in this syntax.
mod_awain1wbin2wcout

我的解法：

module top_module(
input a,
input b,
output out
);
mod_a mod_a0
(
.in1(a),
.in2(b),
.out(out)
);
endmodule

结果正确：

学习内容
表示方法：端口名称或端口位置
mod_a instance1 ( wa, wb, wc );
mod_a instance2 ( .out(wc), .in1(wa), .in2(wb) );