Verilog入门笔记

Verilog笔记

（一）Start

1.basic

Compile Error	编译错误
Simulation Error	编译成功，仿真错误
Incorrect	输出结果错误
Success

---

module top_module( output one );

    assign one = [fixme];

endmodule

代码段开始用module,结束用endmodule

1. output a定义输出信号，input b定义输出信号
2. 连接：assign in = out将out信号线与in连接

assign不同于编程语言的赋值，因为即使右侧的值发生变化，分配也会一直继续。连续分配不是一次性事件

3. 非门(Notgate)

   assign A = ~B表示将B信号取反

4. 与门(Andgate)

   assign A = B&C表示B、C信号相与

5. 或门(Orgate)或非门(Norgate)

   assign A = B|C表示或门，assign A = ~(B|C)表示或非门

6. 异或门(Xnorgate)

   assign out = ~(a^b)

   wire not_in;	 // Declare a wire named "not_in"

2.Vector

​ 向量用于使用一个名称对相关信号进行分组，使调用信号更加便利，定义时需将维度放在向量名之前,但是调用向量中部分维度时维度放在向量名后面。

type [upper:lower] vector_name;	//定义一个向量，'type'为类型，没有特殊说明、类型均为wire
wire [99:0] my_vector;	//Declare a 100-element vector
reg [99:0] my_vector;	//Declare a 100-element vector	'reg'为注册
assign out = my_vector[10];	//Part-select one bit out of the vector
output reg [0:0] y;   // 1-bit reg that is also an output port (this is still a vector)
input wire [3:-2] z;  // 6-bit wire input (negative ranges are allowed)
//writing vec[0:3] when vec is declared wire [3:0] vec; is illegal

• Packed Arrays

  the bits are “packed” together into a blob

  reg [7:0] mem [255:0];   // 256 unpacked elements, each of which is a 8-bit packed vector of reg.
  reg mem2 [28:0];         // 29 unpacked elements, each of which is a 1-bit reg.
  

使用向量名可以访问整个向量

assign w = a;	//如果左右维度不匹配，则自动用0补齐

concatenation operator

{3'b111, 3'b000} => 6'b111000
{1'b1, 1'b0, 3'b101} => 5'b10101
{4'ha, 4'd10} => 8'b10101010     // 4'ha and 4'd10 are both 4'b1010 in binary
//unsized constants are not allowed in concatenations

连接需要知道每一个成员的长度，连接运算符可用于赋值的左侧或右侧

assign {out[7:0], out[15:8]} = in;         // Swap two bytes. Right side and 
assign out[15:0] = {in[7:0], in[15:8]};    // This is the same thing.
assign out = {in[7:0], in[15:8]};       // This is different. The 16-bit vector on the right is extended to
// match the 24-bit vector on the left, so out[23:16] are zero.
                                            // In the first two examples, out[23:16] are not assigned.

If you want the same thing concatenated together many times like a = {b,b,b,b,b,b};?

{num{vector}}	//'num'is the number you want copy
//Examples:
{5{1'b1}}           // 5'b11111 (or 5'd31 or 5'h1f)
{2{a,b,c}}          // The same as {a,b,c,a,b,c}
{3'd5, {2{3'd6}}}   // 9'b101_110_110. It's a concatenation of 101 with