设计数字电路的方法演变
一、反相器
verilog代码
//反相器设计
`timescale 1ns/10ps //1ns为时间单位,10ps的精度
module learning(A, Y);
input A;
output Y;
assign Y=~A;
endmodule
//testbench of inv
module learning_tb;
reg a;
wire y;
learning learning(
.A(a),
.Y(y)
);
initial begin
a<=0;
#10 a<=1;
#10 a<=0;
#10 a<=1;
#10 $stop;
end
endmodule
wire表示直通,即输入有变化,输出马上无条件地反映,reg表示一定要有触发,输出才会反映输入的状态。
在quartus中创建工程后,点击下面的按钮编译:
然后再进行仿真:
右键点击work下的testbench进行simulate:
将参数加人入到波形中:
先点击左边的restart,然后再点击右边的run all:
然后就会出现波形图了:
二、与非门
verilog代码:
//与非门设计
`timescale 1ns/10ps //1ns为时间单位,10ps的精度
module and_not_gate(A, B, Y);
input A,B;
output Y;
assign Y=~(A&B);
endmodule
//testbench of and_not_gate
module and_not_gate_tb;
reg a,b;
wire y;
and_not_gate and_not_gate(
.A(a),
.B(b),
.Y(y)
);
initial begin
a<=0;
b<=0;
#2; //延时2s
a<=1;
b<=0;
#2;
a<=0;
b<=1;
#2;
a<=1;
b<=1;
#2;
$stop;
end
endmodule
波形:
代码:
//与非门设计
`timescale 1ns/10ps //1ns为时间单位,10ps的精度
module and_not_gate(A, B, Y);
input[3:0] A,B;
output[3:0] Y;
assign Y=~(A&B);
endmodule
//testbench of and_not_gate
module and_not_gate_tb;
reg[3:0] a,b;
wire[3:0] y;
and_not_gate and_not_gate(
.A(a),
.B(b),
.Y(y)
);
initial begin
a<=4'b0000;
b<=4'b0000;
#2; //延时2s
a<=4'b1111;
b<=4'b0000;
#2;
a<=4'b0000;
b<=4'b1111;
#2;
a<=4'b1111;
b<=4'b1111;
#2;
$stop;
end
endmodule