【Xilinx】[Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this

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最新推荐文章于 2024-12-12 21:11:20 发布

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[Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets CLK_i_IBUF_inst/O] >
Clock Rule: rule_gclkio_bufg
Status: FAILED
Rule Description: An IOB driving a BUFG must use a GCIO in the same clock region as the BUFG
CLK_i_IBUF_inst/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y172 (in SLR 0)
CLK_i_IBUF_BUFG_inst (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y81 (in SLR 0)
The above error could possibly be related to other connected instances. Following is a list of all the related clock rules and their respective instances.
Clock Rule: rule_bufgce_bufg_conflict Status: PASS Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be used at the same time CLK_i_IBUF_BUFG_inst (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_X0Y81 (in SLR 0) Clock Rule: rule_bufg_driven_by_fabric Status: PASS Rule Description: A BUFGCE clock buffer whose input is driven by a non IO/Clock element should not be placed in BUFGCE_HDIO sites. CLK_i_IBUF_inst/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y172 (in SLR 0) CLK_i_IBUF_BUFG_inst (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_X0Y81 (in SLR 0)