vivodo报[Place 30-675]错误

最近使用VIVODO进行实现时报错

[Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/util_ds_buf_7/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O] >

	design_1_i/util_ds_buf_7/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X1Y112
	 design_1_i/DataStore2Fifo_0/inst/BUFGCE_DIV_inst (BUFGCE_DIV.I) is provisionally placed by clockplacer on BUFGCE_DIV_X0Y8

开始以为是程序代码的问题，后来发现是引脚的问题。
在FPGA中，时钟输入需要专门的时钟引脚。
解决这个问题的办法：
1、将报错的引脚重新约束到FPGA的时钟引脚上，简单来说就是这种六边形的引脚

2、如果引脚不够，可以在约束文件中添加

	< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets design_1_i/util_ds_buf_7/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I/O] >

具体可以看一下报错的Messages. 当然这样相当于屏蔽掉了错误，但是问题不大，对于一般的信号已经够用了。

更详细的说明参见网站https://support.xilinx.com/s/article/66659?language=en_US
和博客。