ERROR: [Place 30-675]

66659 - 2015.4 Vivado Implementation : ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.
Title
66659 - 2015.4 Vivado Implementation : ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.
Description

I see the following error during Implementation. What is the reason for this error and how can I fix it?
ERROR: [Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_in1_IBUF] >
clk_in1_IBUF_inst/IBUFC