Vivad报错-5 [placed 30-675]Sub-optimal placement

已于 2024-07-11 14:28:16 修改
阅读量361 收藏 5
点赞数 3
分类专栏： Vivado进阶 文章标签： fpga开发
于 2024-06-12 17:28:35 首次发布
版权声明：本文为博主原创文章，遵循 CC 4.0 BY-SA 版权协议，转载请附上原文出处链接和本声明。
本文链接：https://blog.csdn.net/weixin_39896700/article/details/139632458
版权

ERROR [placed 30-675] ERROR: Sub-optimal placement for a global clock-capable I0 pin and BUFG pair.   If this sub optimal condition is acceptable for this design, you may use the CLOCK DEDICATED ROUTE constraint in the xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.

<set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets u_dig_io_pad/U_GPIO10/iobuf/0]

        这个错误是在放置器件的时候报出来的，意思就是时钟使能的I/O和全局缓冲器BUFG放置的位置不是最优的。如下图我的设计报错：

        这里的规矩就是一个SLR里面（普及一

了解本专栏 订阅专栏 解锁全文 超级会员免费看
亮锅锅来啦
关注
  • 3
    点赞
  • 踩
  • 5
    收藏
    觉得还不错? 一键收藏
  • 0
    评论
专栏目录
订阅专栏
Vivado报错-3 [Place 30-681]Sub-optimal placement VU19P
weixin_39896700的博客
10-18 1487
管脚所在时钟区域X7Y6，这是需要注意，把所有的MMCM高亮，而且19P的MMCM的后缀并不是他所在的区域，这个具体什么意思我还没时间深究，我刚开始也以为是他的区域导致我以为X7Y6没有MMCM，但是后面高亮之后找到了，就是MMCM_X1Y2如下图，该时钟区域里面包含一个MMCM，即MMCM_X1Y6。接着会报出你的路径吗，一个是你的PLL的路径，一个是你的输入的IO的路径。因为工作比较忙，所以后面就写的比较简略了，最基本的操作会在我前面的文章里面有的，大家有疑问可以看看我前面的文章。
【Xilinx】[Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this
sqqwm的专栏
05-28 811
[Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However
[Place 30-575] | [Place 30-675] Sub-optimal placement for a clock-capable IO pin and MMCM pair
qq_41544116的博客
07-13 2960
我出现了第一种，是在配置 ddr 时使用的 mmcm 的报错，mmcm(Clocking Wizard) 的 Clock Options/Input Clock Information 里的 Source 配置了 Single ended clock capable pin，然后就出错了。时钟引脚用的是带有MRCC标志的，也就是 I/O Planning 里的六边形的引脚。如果此设计可接受此次优条件，则可以使用.xdc文件中的CLOCK_DEDICATED_ROUTE约束将此消息降级为“警告”。
Vivad报错-5_2 [placed 30-675]Sub-optimal placement
最新发布
weixin_39896700的博客
06-17 257
Vivad报错 [placed 30-675] Sub-optimal placement
Vivado2020.1 ERROR: [Place 30-681] Sub-optimal placement for a global clock-capable IO pin and MMCM
WillDuo的博客
11-30 3758
全局时钟IO管脚和MMCM之间非最优布局。为了解决这错误，可在IO和MMCM之间插入BUFG。 IO锁定在IOB_X1Y132 （在SLR 0区域） MMCM被时钟布局引擎暂时放置在MMCME3_ADV_X1Y5 （在SLR1区域）
Vivado报错 Place 30-675 Sub-optimal for a global clock-capable IO pin
yundanfengqing_nuc的专栏
08-20 1552
文中网址：https://china.xilinx.com/support/answers/66659.html ...
A Correlation-aware Diverse Variant Placement to Increase Network Resilience
02-08
For example, diverse variants are placed to nodes in the network. However, the existing works assume that diverse variants do not have common vulnerabilities, which is an invalid assumption in some ...
Multi-Core Cache Hierarchies
04-14
cache resources must be allocated across many cores, data must be placed in cache banks that are near the accessing core, and the most important data must be identified for retention. Finally, diffi...
Feature-based 3D reconstruction of fabric by binocular stereo-vision
02-09
Generally, image-... Concretely, two parallel-placed digital cameras were calibrated based on planar pattern and the captured binocular images were rectified through epipolar line. The feature points
K-均值聚类算法研究
07-04
It is a point-based clustering method that starts with the cluster centers initially placed at arbitrary positions and proceeds by moving at each step the cluster centers in order to minimize the ...
Heterogeneous Networks in LTE-Advanced
02-03
The authors, being involved in LTE standardization, are well placed to give an excellent view on this topic, including valuable background and design rationale. A comprehensive summary of wireless...
在Vivado 2020.1中用MIG核读写DDR3内存，编译代码时提示Sub-optimal placement错误的解决办法
ZLK1214的专栏
11-19 7101
板子使用的是米联客的XC7A35TFGG484-2的开发板，上面带有256MB的型号为Micron MT41K128M16的DDR3内存。板子上的V4引脚上接了50MHz的晶振。 用MIG核来驱动这片DDR3内存。DDR3的运行时钟Clock Period为400MHz： PLL Input Clock Period（sys_clk_i）为200MHz： sys_clk_i和clk_ref_i都配置为No Buffer，然后在代码中都共用同一个200MHz的时钟： .sys_clk_i(
ERROR: [Place 30-675]
leonzheng的博客
12-06 1054
vivado error 30-675
VIVADO [place 30-675]错误
inorisama的博客
11-28 385
按照官方解释，就算接入的IO的不是一个CLK，当需要给IO插入BUFG时，也同样可能因为rule_bufgce_bufg_conflict检查报错。
vivodo报[Place 30-675]错误
qq_33361431的博客
06-05 2873
最近使用VIVODO进行实现时报错 开始以为是程序代码的问题，后来发现是引脚的问题。 在FPGA中，时钟输入需要专门的时钟引脚。 解决这个问题的办法： 1、将报错的引脚重新约束到FPGA的时钟引脚上，简单来说就是这种六边形的引脚 2、如果引脚不够，可以在约束文件中添加 具体可以看一下报错的Messages. 当然这样相当于屏蔽掉了错误，但是问题不大，对于一般的信号已经够用了。更详细的说明参见网站https://support.xilinx.com/s/article/66659?language=en_U
遇见BUG（1）：都是非时钟专用引脚惹的祸？
热门推荐
Reborn Lee
11-06 1万+
最近遇到一个问题，就是在使用FPGA上的一对差分时钟的时钟，总是提示这样的错误： [Place 30-172] Sub-optimal placement for a clock-capable IO pin and PLL pair. If this sub optimal condition is acceptable for this design, you may use the CL...
Xilinx Clock Wizard注意事项
一个早起的程序员
03-03 1887
1个时钟，不能连接到2个Clock Wizard IP上，会报错，如下： 54962 - Vivado Implementation - ERROR: [Place 30-120] Sub-optimal placement for a BUFG-BUFG cascade pair.
[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk_IBUF] > sys_clk_IBUF_inst (IBUF.O) is locked to IOB_X1Y74 instance_name/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2 The above error could possibly be related to other connected instances. Following is a list of all the related clock rules and their respective instances. Clock Rule: rule_mmcm_bufg Status: PASS Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device instance_name/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2 and instance_name/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31
07-11
Based on the provided information, it seems that there is a sub-optimal placement for a clock-capable IO pin and MMCM pair in your design. If this condition is acceptable, you can use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote the message to a WARNING. However, using this override is highly discouraged. To override this clock rule, you can add the following line in the .xdc file: ``` set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk_IBUF] ``` Please note that this error could possibly be related to other connected instances. The related clock rule "rule_mmcm_bufg" seems to be passing, but it's important to review all the clock rules and their respective instances to ensure proper placement. If you have any further questions or need additional assistance, feel free to ask.
评论
添加红包

请填写红包祝福语或标题

个

红包个数最小为10个

元

红包金额最低5元

当前余额3.43元 前往充值 >
需支付：10.00元
成就一亿技术人!
领取后你会自动成为博主和红包主的粉丝 规则
hope_wisdom
发出的红包
实付元
使用余额支付
点击重新获取
扫码支付
钱包余额 0

抵扣说明：

1.余额是钱包充值的虚拟货币，按照1:1的比例进行支付金额的抵扣。
2.余额无法直接购买下载，可以购买VIP、付费专栏及课程。

余额充值