除法器FPGA实现

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2017/08/18 15:20:41
// Design Name: 
// Module Name: devided
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module devided(
                clk,
                rst_n,
                a,
                b,
                result,
                remainder
    );
    
    input                 clk;
    input                 rst_n;
    
    input   [15:0]        a;   // 被除数
    input   [7:0]         b;   //除数
    
    output  reg  [15:0]        result; // 商
    output    [7:0]         remainder;//余数
    
    reg    [22:0]        mid_a ;
    reg    [2:0]         state;
    reg    [6:0]         diff;
    reg    [4:0]         cnt;
    
    always@(posedge clk or negedge rst_n) begin
        if(!rst_n)begin
            mid_a <= {7'd0