top.sv
program automatic test;
import uvm_pkg::*;
class hello_world extends uvm_test;
`uvm_component_utils(hello_world);
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction
virtual task run_phase(uvm_phase phase);
`uvm_info("TEST", "hello_world", UVM_MEDIUM);
endtask
endclass
initial begin
run_test();
end
endprogram
all:clean comp run
comp:
vcs -sverilog -ntb_opts uvm-1.1 hello.sv
run:
./simv +UVM_TESTNAME=hello_world +UVM_VERBOSITY=UVM_DEBUG
clean:
rm -rf csrc simv simv.daidir ucli.key vc_hdrs.h
result:
UVM_INFO @ 0: reporter [RNTST] Running test hello_world...
UVM_INFO hello.sv(13) @ 0: uvm_test_top [TEST] hello_world
test