0.属性定义
1.获取die的坐标
2.获取core的宽度 高度
一、计算macro区域
二、创建routing blockage for power
主要不想让让macro上横跨power stripe
三、创建 power rail
### create power rails (Metal1)
setAddStripeMode -reset
setAddStripeMode -stacked_via_bottom_layer Metal1 -stacked_via_top_layer Metal1
addStripe -nets { VDD } -layer Metal1 -direction horizontal -width 0.120 -spacing 1.710 -set_to_set_distance 3.420 -start [expr 1.71 - 0.120 / 2.0] -stop $die_y1 -area $die_area -area_blockage $macro_region
addStripe -nets { VSS } -layer Metal1 -direction horizontal -width 0.120 -spacing 1.710 -set_to_set_distance 3.420 -start [expr 1.71*2 - 0.120 / 2.0] -stop $die_y1 -area $die_area -area_blockage $macro_region
注:在设置mode前一般都reset 重置一下
四、在macro周围创建power ring
setAddRingMode -reset
deselectAll
selectInst [dbGet [dbGet top.insts.cell.subClass block -p2].name]
setAddRingMode -stacked_via_bottom_layer Metal1 -stacked_via_top_layer Metal9
addRing -nets {VDD VSS} -type block_rings -around selected -layer {top Metal9 bottom Metal9 left Metal8 right Metal8} -width {top 5 bottom 5 left 5 right 5} -spacing {top 1.25 bottom 1.25 left 1.25 right 1.25
1.重置mode
2.抓取macro
3.设置mode
4.addRing
五、加power stripe
### create power stripes (Metal8 and Metal9)
#editDelete -use {POWER} -shape {RING STRIPE FOLLOWPIN IOWIRE COREWIRE BLOCKWIRE PADRING BLOCKRING FILLWIRE FILLWIREOPC DRCFILL}
setAddStripeMode -reset
setAddStripeMode -break_at {block_ring} -stacked_via_bottom_layer Metal1 -stacked_via_top_layer Metal9
addStripe -nets {VDD VSS} -layer Metal9 -direction horizontal -width 5 -spacing 1.25 -set_to_set_distance 72 -start_from bottom -start_offset 40 -stop_offset 0 -block_ring_top_layer_limit Metal9 -block_ring_bottom_layer_limit Metal1
setAddStripeMode -reset
setAddStripeMode -break_at {block_ring} -stacked_via_bottom_layer Metal1 -stacked_via_top_layer Metal9
addStripe -nets {VDD VSS} -layer Metal8 -direction vertical -width 5 -spacing 1.25 -set_to_set_distance 75 -start_from left -start_offset 35 -stop_offset 0 -block_ring_top_layer_limit Metal9 -block_ring_bottom_layer_limit Metal1
六、保存设计
saveDesign ..
七、检查
1.verify_drc
2.verifyConnectivity
这里为假错,暂时可以忽略
3.checkplae
tee 就是直接检查checkplace 并且就输入到该路径成为报告