使用Synopsys VCS仿真Vivado FIFO IP

导语

使用VCS仿真FIFO IP时，出现如下VHDL syntactic or semantic error/warnings错误，如何处理呢？

Info-[SYNTAX-ENCRYPTED]  VHDL syntactic or semantic error/warnings detected in the encrypted source 
  file ./../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd.  The actual error
  message has been suppressed for security reasons.  Please contact the vendor
  of this file for resolution of this problem

Vivado 生成 FIFO IP

1. File --> IP --> New Location… (见 Figure 1)
2. New IP Location --> Next --> Mange IP Settings (见图2)
   • part : xilinx芯片类型
   • Target language: verilog / vhdl
   • Target Simulatior: 目标仿真器（Vivado simulator/ modelsim / VCS / Incisive / Xcelium等可供选择）
   • Simlator language : Mixed / verilog /vhdl (说明仿真只有verilog文件, 只有vhdl文件或者 verilog + VHDL)
   • IP location : 指定产生IP的位置
3. IP Catalog （见图3）

Figure 1: New IP

Figure 2: IP settings

Figure 3: FIFO IPs

Vivado 编译 pre-compiled libraries

参考：xilinx support
在vivado中使用compile_simlib命令编译Xilinx Simulation libraries.

Batch Mode

• Project Mode
  From the Tcl Console, run: compile_simlib -simulator vcs
  注： 本人没有测试过！
• Non-Project Mode
  先打开vivado：vivado -mode tcl；
  然后，vivado tcl console, 输入

  compile_simlib -simulator vcs \
             -simulator_exec_path {/home/EDAtools/Synopsys/VCSMX/O-2018.09/bin} \
             -gcc_exec_path {/opt/rh/devtoolset-9/root/usr/bin} \
             -family kintex7 -language all -library all \
             -dir {../ipcores/managed_ip_project/managed_ip_project.cache/compile_simlib/vcs}
  

  注：
  1. -simulator_exec_path : vcs启动路径
  2. -gcc_exec_path : gcc可执行文件路径
  3. -family： 此处只选择了kintex7
  4. -library : 选择了所有(不知道需要那些，全部编译)
  5. -dir : compile_simlib的输出位置

Gui Mode

1. 打开vivado , GUI模式
2. 选择tools --> Compile Simulation Libraries,打开一下对话框：
   

使用VCS仿真

无 pre-compile libraries

编译fifo_generator_v13_2_rfs.vhd文件时，如下错误出现多次：

Parsing design file './../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd'
Info-[SYNTAX-ENCRYPTED]  VHDL syntactic or semantic error/warnings detected in the encrypted source 
  file ./../../../ipstatic/hdl/fifo_generator_v13_2_rfs.vhd.  The actual error
  message has been suppressed for security reasons.  Please contact the vendor
  of this file for resolution of this problem

添加pre-compile libraries

使用synopsys_sim.setup文件中添加了pre-compile libraries，就不会出现上述的错误。

Reference

1. Failure to compile FIFO Generator v13.0
2. Compile Simulation Library
3. synopsys_sim.setup