VCS编译xilinx IP核

1. 背景

vivado2018.03
vcs O-2018.09-SP2

2. 出现的问题

2.1 vivado编译IP库时显示版本不对

ERROR: [Vivado 12-4686] Simulator version check command failed:"/home/fpga-0/software/synopsys2018/vcs_2018.09/bin/vlogan -ID -full64". Please make sure that this version of simulator support the options specified in this command. For more details on this failure, open the '.cxl.vcs_mx.version' file.
ERROR: [Vivado 12-4688] Unsupported simulator version. Please run 'compile_simlib -help' for the supported 'vlogan script version' version.

解决方案：

1. 确实是版本不匹配，我的vcs版本一开始是2016.06，他就不支持Vivado2018.03
2. 用命令行开启vivado，这是在网上查出来一个说开启管理员模式解决了这个问题。我一开始是通过点击Vivado图标的方式启动的，但是一直报版本不匹配这个问题，最后通过命令行启动，这个问题解决了

2.2 vhdlan编译一直报错

ERROR - can't find /home/fpga-0/software/synopsys2018/vcs_2018.09/linux/bin/vhdlan1, check installation.
        exiting ...

这个问题是vhdlan使用方法错误，如果安装的是linux64的版本，在使用vhdlan时一定要加上-full64的参数

2.3 编译报错undefined identifier

Error-[OVNOSELECT1_LIB] Undefined identifier
/home/fpga-0/NGS_prj/UVM/matrix7_uvm/rtl/lib/self_iplib/fifo_512x512.vhd, 57
FIFO_512X512
  
  USE fifo_generator_v13_2_3.fifo_generator_v13_2_3;
                             ^
  The symbol named 'FIFO_GENERATOR_V13_2_3' cannot be found in library 
  'FIFO_GENERATOR_V13_2_3'.


Error-[IEEEVHDLNOENT] Missing compiled design unit
/home/fpga-0/NGS_prj/UVM/matrix7_uvm/rtl/lib/self_iplib/fifo_512x512.vhd, 74
analysis-Parsing, "FIFO_512X512"
  
  ARCHITECTURE fifo_512x512_arch OF fifo_512x512 IS
                                    ^
  The compiled design unit for entity 'FIFO_512X512' is not found in WORK 
  library.

这个问题目前还没有解决，首先我已经把synopsys_sim.setup文件复制到脚本所在的文件夹下了，并且我编译加法器和减法器的.vhd文件是没有报错的，.setup文件是起了作用的。这是.setup文件下的IP映射

fifo_generator_v13_2_3 : /home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3

这是该路径下的IP编译的库

/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.verilog.fifo_generator_v13_2_3.fifo_generator_v13_2_3.lin64.cmd
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.verilog.fifo_generator_v13_2_3.fifo_generator_v13_2_3.lin64.cmf
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.verilog.fifo_generator_v13_2_3.fifo_generator_v13_2_3.lin64.rpt
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.vhdl.fifo_generator_v13_2_3.fifo_generator_v13_2_3.lin64.cmd
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.vhdl.fifo_generator_v13_2_3.fifo_generator_v13_2_3.lin64.cmf
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/.cxl.vhdl.fifo_generator_v13_2_3.fifo_generator_v13_2_3.lin64.rpt
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/64
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/64/.vhdl_lib_lock
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/64/vhdl.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/64/vhmra.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/.vcs_lib_lock
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/AllModulesSkeletons.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/compat.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/debug_dump
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/dumpcheck.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/dve.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/make.vlogan
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/modfilename.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/str.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/str.index.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/str.info.db
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/vir.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/vir_global.sdb
/home/fpga-0/NGS_prj/minimap_fpga_PU8/minimap_fpga.cache/compile_simlib/vcs/fifo_generator_v13_2_3/AN.DB/vloganopts.db

目前这个问题还没有解决，我在xilinx社区上提了一下遇到的问题，可以确定的是setup文件是起了作用的，IP库我看了一下也是确定编译正确0error和0warning的，目前想不出可能哪里出现了问题，先总结成这样吧。