PCIe 书籍

高速总线基础
PCIe

https://blog.csdn.net/BtB5e6Nsu1g511Eg5XEg/article/details/88386645

https://blog.csdn.net/u010872301/article/details/78519371

https://blog.csdn.net/Ivan804638781/article/details/81281353

https://www.bilibili.com/video/av66250574

https://developer.arm.com/architectures/system-architectures/amba/pcie

https://github.com/IMCG/-/blob/master/hardware/PCI_PCI-X_PCI-E.md

https://i4k.xyz/article/weixin_42491720/125809177


https://pcisig.com/


https://blog.csdn.net/icxiaoge/article/details/123602107

https://blog.csdn.net/DSMGUOGUO/article/details/125983803



 pci express system architecture_200page.pdf 


PCI Express 体系结构导读				 2.0
PCI、PCI-X和PCI Express的原理及体系结构	 1.0

《PCI Express体系结构导读》
《PCI、PCI-X和PCI Express的原理及体系结构》

《PCI、PCI-X和PCI Express的原理及体系结构》初版时间更早,只讲解了第一代PCIE协议,速率只有2.5Gbps单lane。不过此书通俗易懂,是中文版入门的绝佳教材。

《PCI Express体系结构导读》讲解了第二代PCIE协议,速率为5Gbps单lane,虽然只讲解了第二代协议内容,但是已经包含了绝大部分PCIE协议内容。此书如果没有PCIE相关基础,阅读起来会比较苦涩难懂。

《MindShare PCI Express Technology 3.0》是MindShare公司推迟的英文版PCIE教材,图文并茂,通俗易懂,可以说是PCIE相关IC designer的必读书籍,强烈推荐。


高速串行总线基础技术
LTSSM状态机(链路训练)
Serdes 

Traditional multi-drop, parallel bus technology is approaching its practical performance limits. It is clear that balancing system performance requires I/O bandwidth to scale with processing and application demands. There is an industry mandate to re-engineer I/O connectivity within cost constraints. PCI Express comprehends the many I/O requirements presented across the spectrum of computing and communications platforms, and rolls them into a common scalable and extensible I/O industry specification. Alongside these increasing performance demands, the enterprise server and communications markets have the need for improved reliability, security, and quality of service guarantees. This specification will therefore be applicable to multiple market segments. Technology advances in high-speed, point-to-point interconnects enable us to break away from the bandwidth limitations of multi-drop, parallel buses. The PCI Express basic physical layer consists of a differential transmit pair and a differential receive pair. Dual simplex data on these point-to-point connections is self-clocked and its bandwidth increases linearly with interconnect width and frequency. PCI Express takes an additional step of including a message space within its bus protocol that is used to implement legacy “side- band” signals. This further reduction of signal pins produces a very low pin count connection for components and adapters. The PCI Express Transaction, Data Link, and Physical Layers are optimized for chip-to-chip and board-to-board interconnect applications. An inherent limitation of today’s PCI-based platforms is the lack of support for isochronous data delivery, an attribute that is especially important to streaming media applications. To enable these emerging applications, PCI Express adds a virtual channel mechanism. In addition to use for support of isochronous traffic, the virtual channel mechanism provides an infrastructure for future extensions in supporting new applications. By adhering to the PCI Software Model, today’s applications are easily migrated even as emerging applications are enabled.
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