PCIe 总线的拓扑

PCI Express Technology 3.0 P145

Definition of Bus, Device and Function

Just as in PCI, every PCIe Function is uniquely identified by the Device it resides within and the Bus to which the Device connects. This unique identifier is commonly referred to as a ‘BDF’. Configuration software is responsible for detecting every Bus, Device and Function (BDF) within a given topology. The following sections discuss the primary BDF characteristics in the context of a sample PCIe topology. Figure 3‐1 on page 87 depicts a PCIe topology that highlights the Buses, Devices and Functions implemented in a sample system. Later in this chapter the process of assigning Bus and Device Numbers is explained.

PCIe Buses

Up to 256 Bus Numbers can be assigned by configuration software. The initial Bus Number, Bus 0, is typically assigned by hardware to the Root Complex. Bus 0 consists of a Virtual PCI bus with integrated endpoints and Virtual PCI‐to‐PCI Bridges (P2P) which are hard‐coded with a Device number and Function number. Each P2P bridge creates a new bus that additional PCIe devices can be connected to. Each bus must be assigned a unique bus number. Configuration software begins the process of assigning bus numbers by searching for bridges starting with Bus 0, Device 0, Function 0. When a bridge is found, software assigns the new bus a bus number that is unique and larger than the bus number the bridge lives on. Once the new bus has been assigned a bus number, software begins looking for bridges on the new bus before continuing scanning for more bridges on the current bus. This is referred to as a “depth first search” and is described in detail in “Enumeration ‐ Discovering the Topology” on page 104.

PCIe Devices

PCIe permits up to 32 device attachments on a single PCI bus, however, the point‐to‐point nature of PCIe means only a single device can be attached directly to a PCIe link and that device will always end up being Device 0. Root Complexes and Switches have Virtual PCI buses which do allow multiple Devices being “attached” to the bus. Each Device must implement Function 0 and may contain a collection of up to eight Functions. When two or more Functions are implemented the Device is called a multi‐function device.

PCIe Functions

As previously discussed Functions are designed into every Device. These Functions may include hard drive interfaces, display controllers, ethernet controllers, USB controllers, etc. Devices that have multiple Functions do not need to be implemented sequentially. For example, a Device might implement Functions 0, 2, and 7. As a result, when configuration software detects a multifunction device, each of the possible Functions must be checked to learn which of them are present. Each Function also has its own configuration address space that is used to setup the resources associated with the Function.

PCIe 拓扑图

在这里插入图片描述

PCIe 拓扑实例

你可以任意找一台 这几年 的x86机器,然后lspci 看一下
Contents OBJECTIVE OF THE SPECIFICATION............................................................................... 23 DOCUMENT ORGANIZATION.............................................................................................. 23 DOCUMENTATION CONVENTIONS................................................................................... 24 TERMS AND ACRONYMS ...................................................................................................... 25 REFERENCE DOCUMENTS................................................................................................... 32 1. INTRODUCTION............................................................................................................... 33 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 33 1.2. PCI EXPRESS LINK......................................................................................................... 35 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 37 1.3.1. Root Complex........................................................................................................ 37 1.3.2. Endpoints .............................................................................................................. 38 1.3.3. Switch.................................................................................................................... 41 1.3.4. Root Complex Event Collector.............................................................................. 42 1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 42 1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION ....................................................... 42 1.5. PCI EXPRESS LAYERING OVERVIEW........................................................................
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