module top_module(
input clk,
input [7:0] in,
input reset, // Synchronous reset
output done); //
reg b3;
assign b3 = in[3];
parameter BYTE1 = 4'b0001;
parameter BYTE2 = 4'b0010;
parameter BYTE3 = 4'b0100;
parameter DONE = 4'b1000;
reg [3:0] state, next;
// State transition logic (combinational)
always @(*) begin
if(reset ==0) begin
case (state)
BYTE1: begin
if(b3)
next = BYTE2;
else
next = BYTE1;
end
BYTE2: begin
next = BYTE3;
end
BYTE3: begin
next = DONE;
end
DONE : begin
if(b3)
next = BYTE2;
else
next = BYTE1;
end
default: begin
next = BYTE1;
end
endcase
end
else
next = BYTE1;
end
// State flip-flops (sequential)
always @(posedge clk) begin
if(reset)
state = BYTE1;
else
state = next;
end
// Output logic
assign done = (state == DONE)? 1'b1: 1'b0;
endmodule
hdlbits.01xz.net /Circuits/Sequential Logic/Finite State Machines/PS/2 packet parser
最新推荐文章于 2024-09-13 16:59:02 发布