hdlbits.01xz.net /Circuits/Sequential Logic/Finite State Machines/Q2a: FSM

module top_module (
    input clk,
    input resetn,    // active-low synchronous reset
    input [3:1] r,   // request
    output [3:1] g   // grant
); 
    parameter A = 4'b0001;
    parameter B = 4'b0010;
    parameter C = 4'b0100;
    parameter D = 4'b1000;
    
    reg [3:0] state, next;
    
    //ff
    always @(posedge clk) begin
        if(!resetn)
            state = A;
        else
            state = next;
    end
    
    //trans
    always @(*) begin
        if(!resetn)
            next = A;
        else begin
            case (state)
                A:begin
                    if(r[1])
                        next = B;
                    else if(r[2])
                        next = C;
                    else if(r[3])
                        next = D;
                    else
                        next = A;
                end
                B: begin
                    if(r[1])
                        next = B;
                    else
                        next = A;
                end
                C: begin
                    if(r[2])
                        next = C;
                    else
                        next = A;
                end
                D: begin
                    if(r[3])
                        next = D;
                    else
                        next = A;
                end
                default:
                    next = A;
            endcase
        end 
    end
    
    //out
    assign g[1] = (state==B)? 1: 0;
    assign g[2] = (state==C)? 1: 0;
    assign g[3] = (state==D)? 1: 0;

endmodule