module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = (a|b|c|d)&(a|b|c|~d)&(~a|b|c|d)&(~a|b|c|~d); // Fix me
endmodule
hdlbits.01xz.net /Verification:Reading Simulations/Build a circuit from a simulation waveform/C.4.
最新推荐文章于 2024-05-31 22:50:46 发布