module top_module (
input clk,
input a,
output [2:0] q );
always @ (posedge clk) begin
if(a == 0) begin
if(q < 6)
q = q+3'd1;
else
q = 0;
end
else begin
q = 4;
end
end
endmodule
hdlbits.01xz.net /Verification:Reading Simulations/Build a circuit from a simulation waveform/S.9.
最新推荐文章于 2024-06-07 23:17:16 发布