【verilog学习24】HDLBits：Verification:Reading Simulations_Build a circuit from a simulation waveform

I Combinational circuit 1 (Sim/circuit1)

1.代码编写

module top_module (
    input a,
    input b,
    output q );//

    assign q = a&b; // Fix me

endmodule

2.提交结果

Success

3.题目分析

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

这是一个“与”逻辑。

II Combinational circuit 2 (Sim/circuit2)

1.代码编写

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = ~(a^b)&~(c^d) || (a^b)&(c^d); // Fix me

endmodule

2.提交结果

Success

3.题目分析

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

III Combinational circuit 3 (Sim/circuit3)

1.代码编写

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = !(!a&!b | !c&!d); // Fix me

endmodule

2.提交结果

Success

3.题目分析

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

IV Combinational circuit 4 (Sim/circuit4)

1.代码编写

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//

    assign q = b&!c | c; // Fix me

endmodule

2.提交结果

Success

3.题目分析

This is a combinational circuit. Read the simulation waveforms to determine what the circuit does, then implement it.

V Combinational circuit 5 (Sim/circuit5)

1.代码编写

module top_module (
    input [3:0] a,
    input [3:0] b,
    input [3:0] c,
    input [3:0] d,
    input [3:0] e,
    output [3:0] q );
    always@(*) begin
        if(c == 4'd0)
            q = b;
        else if(c == 4'd1)
            q = e;
        else if(c == 4'd2)
            q = a;
        else if(c == 4'd3)
            q = d;
        else
            q = 4'hf;
    end
endmodule

2.提交结果

Success

3.题目分析

分析作用：当c=0，1，2，3时，q=b，e，a，d的输入值。
否则，q=4‘hf。
波形无延迟，为组合赋值。
（用case语句也行）

VI Combinational circuit 6 (Sim/circuit6)

1.代码编写

module top_module (
    input [2:0] a,
    output [15:0] q ); 
    always@(*) begin
        case(a)
            3'd0: q = 16'h1232;
            3'd1: q = 16'haee0;
            3'd2: q = 16'h27d4;
            3'd3: q = 16'h5a0e;
            3'd4: q = 16'h2066;
            3'd5: q = 16'h64ce;
            3'd6: q = 16'hc526;
            3'd7: q = 16'h2f19;
            default: q = 16'h1232;
        endcase
    end
endmodule

2.提交结果

Success

3.题目分析

VII Sequential Circuit 7 (Sim/circuit7)

1.代码编写

module top_module (
    input clk,
    input a,
    output q );
    always@(posedge clk) begin
        q <= ~a;
    end
endmodule

2.提交结果

Success

3.题目分析

VIII Sequential Circuit 8 (Sim/circuit8)

1.代码编写

module top_module (
    input clock,
    input a,
    output p,
    output q );
    always@(*) begin
        p = (clock)? a:p;
    end
    always@(negedge clock) begin
        q <= a;
    end
endmodule

2.提交结果

Success

3.题目分析

可见，
p：在clock高电平对a输出，低电平进行锁存。
q：在clock下降沿对a输出。

IX Sequential Circuit 9 (Sim/circuit9)

1.代码编写

module top_module (
    input clk,
    input a,
    output [3:0] q );
    always@(posedge clk) begin
        if(a)
            q <= 4'd4;
        else begin
            q <= (q == 4'd6)? 4'd0:q + 4'd1;
        end
    end
endmodule

2.提交结果

Success

3.题目分析

• 时钟上升沿触发。
• 在a=1时，输出q<=4’d4。
• 在a=0时，进行6进制向上计数。

X Sequential Circuit 10 (Sim/circuit10)

1.代码编写

module top_module (
    input clk,
    input a,
    input b,
    output q,
    output state  );
    always@(posedge clk) begin
        state <= (a == b)? a:state;        
    end
    assign q = (a == b)? state:!state;
endmodule

2.提交结果

Success

3.题目分析

时序：当a=b，state<=a，当a不等b，state锁存。
组合：当a=b，q=state，当a不等b，q=!state。
时序输出state辅助组合输出。