hdlbits.01xz.net /Verification:Reading Simulations/Build a circuit from a simulation waveform/S.10.

module top_module (
    input clk,
    input a,
    input b,
    output q,
    output state  );
    
    always @(posedge clk) begin
        if((a==1)&(b==1)) 
            state = 1;
        else if ((a==0)&(b==0)) 
            state = 0;
        else 
            state = state;
    end
    
    always @(*) begin
        if(state)
            q = ~(a^b);
        else
            q = (a^b);
    end
endmodule