module top_module (
input clock,
input a,
output p,
output q );
assign p = clock? a: p;
initial begin
q = 1;
end
always @(negedge clock) begin
q=a;
end
endmodule
hdlbits.01xz.net /Verification:Reading Simulations/Build a circuit from a simulation waveform/S.8.
最新推荐文章于 2024-06-07 23:17:16 发布