【西西学FPGA】Lesson14 fifo

Lesson 14
2016.4.16
内容：
rx+fifo+compute+tx

要点：
1 第一行 0-85 给fifo0
2 第二行 0-85 给fifo1
3 第三行 0-85 与fifo0 、fifo1 做计算，同时传给fifo1；
4 第四行如上，且 fifo1 输入满85以后，再读取新的数字，同时将值给fifo0；

5 fifo，同时读写，无需地址，在请求来的下一个时钟有效。

易错点：
1 wrreq_0 的控制条件
2 num_cnt第一次计数清零的条件
3 模块的输入输出划分；

关键代码如下：

module fifo(
        input wire sclk,
        input wire s_rst_n,
        input wire rx_flag_tmp,
        input wire [7:0] rx_num_tmp,
        
        output reg [7:0] tx_num,
        output reg tx_flag
        );

        reg [7:0] num_cnt;
        reg [7:0] all_cnt;
        reg [7:0] data_0;
        reg [7:0] data_1;
        reg rdreq_0;
        reg wrreq_0;
        reg rdreq_1;
        reg wrreq_1;
        
        reg [7:0] rx_num;
        reg rx_flag;
        reg [7:0] rx_num_1;
        reg rx_flag_1;
        
        
        wire [7:0] q_0 ;
        
        
        
        wire [7:0] q_1 ;
        
//rx_num
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                rx_num <= 8'd0;
        else
                rx_num <= rx_num_1;
//rx_flag
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                rx_flag <= 1'b0;
        else
                rx_flag <= rx_flag_1;
//rx_num_1
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                rx_num_1 <= 8'd0;
        else
                rx_num_1 <= rx_num_tmp;
                
//rx_flag_1
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                rx_flag_1 <= 1'b0;
        else
                rx_flag_1 <= rx_flag_tmp;
                
//num_cnt
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                num_cnt <= 8'd0;
        else if (all_cnt == 8'd0)
                begin
                        if ((num_cnt == 8'd86)&&(rx_flag_tmp == 1'b1))
                                num_cnt <= 8'd0;
                        else if(rx_flag_tmp == 1'b1)
                                num_cnt <= num_cnt + 1'b1;
                end
        else if(all_cnt >= 8'd1)
                begin
                        if ((num_cnt == 8'd85)&&(rx_flag_tmp == 1'b1))
                                num_cnt <= 8'd0;
                        else if(rx_flag_tmp == 1'b1)
                                num_cnt <= num_cnt + 1'b1;
                end
//all_cnt
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                all_cnt <= 8'd0;
        else if ((all_cnt == 8'd0)&&(num_cnt == 8'd86)&&(rx_flag_tmp == 1'b1))
                all_cnt <= all_cnt + 1'b1;
        else if ((all_cnt >= 8'd1)&&(num_cnt == 8'd85)&&(rx_flag_tmp == 1'b1))
                all_cnt <= all_cnt + 1'b1;
                
//tx_num
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                tx_num <= 8'd0;
        else if ((all_cnt >= 8'd2)&&(rx_flag == 1'b1))
                tx_num <= q_0 + q_1 + rx_num_tmp;

//tx_flag
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                tx_flag <= 1'b0;
        else if ((all_cnt >= 8'd2)&&(rx_flag == 1'b1))
                tx_flag <= 1'b1;
        else
                tx_flag <= 1'b0;
//data_0;
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                data_0 <= 8'd0;
        else if ((all_cnt == 8'd0)&&(rx_flag_tmp == 1'b1))
                data_0 <= rx_num_tmp;
        else if (((all_cnt >= 8'd2 )&&(rx_flag == 1'b1))||((all_cnt == 8'd1)&&(num_cnt == 8'd85)&&(rx_flag_tmp == 1'b1)))
                data_0 <= q_1;
//data_1;
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                data_1 <= 8'd0;
        else if((all_cnt >= 8'd1)&&(rx_flag_tmp == 1'b1))
                data_1 <= rx_num_tmp;

//rdreq_0;
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                rdreq_0 <= 1'b0;
        else if(((all_cnt >= 8'd2)&&(rx_flag_tmp == 1'b1))||((all_cnt == 8'd1)&&(num_cnt == 8'd85)&&(rx_flag_tmp == 1'b1)))
                rdreq_0 <= 1'b1;
        else
                rdreq_0 <= 1'b0;
//wrreq_0;
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                wrreq_0 <= 1'b0;
        //||(all_cnt >=8'd2)||((all_cnt == 8'd1)&&(num_cnt == 8'd85)))
        else if ((all_cnt == 8'd0)&&(num_cnt <= 8'd85)&&(rx_flag_tmp == 1'b1))
                wrreq_0 <= 1'b1;
        else if ((all_cnt >= 8'd2)&&(rx_flag == 1'b1))
                wrreq_0 <= 1'b1;
        else
                wrreq_0 <= 1'b0;
                
//rdreq_1;
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                rdreq_1 <= 1'b0;
        else if(((all_cnt >= 8'd2)&&(rx_flag_tmp == 1'b1))||((all_cnt == 8'd1)&&(num_cnt == 8'd85)&&(rx_flag_tmp == 1'b1)))
                rdreq_1 <= 1'b1;
        else
                rdreq_1 <= 1'b0;
//wrreq_1;
always@(posedge sclk or negedge s_rst_n)
        if(!s_rst_n)
                wrreq_1 <= 1'b0;
        else if (((all_cnt >=8'd1)||((all_cnt == 8'd0)&&(num_cnt == 8'd86)))&&(rx_flag_tmp == 1'b1))
                wrreq_1 <= 1'b1;
        else
                wrreq_1 <= 1'b0;

 fifo_8x128 fifo_8x128_0(
        .clock (sclk) ,
        .data (data_0) ,
        .rdreq (rdreq_0) ,
        .wrreq (wrreq_0) ,
        
        
        .q (q_0 )
        );
        
fifo_8x128 fifo_8x128_1(
        .clock (sclk) ,
        .data (data_1) ,
        .rdreq (rdreq_1) ,
        .wrreq (wrreq_1) ,
        
        
        .q (q_1)
        );

结果的波形图，需要质疑wrreq_0 跳变的条件