【FPGA】【Verilog】【基础模块】“阻塞”与非阻塞”的对比

module blocking(clk,a,b,c);
	output [3:0] b,c;
	input [3:0] a;
	input clk;
	
	reg [3:0] b,c;
	
	always @(posedge clk)
		begin
			b = a;
			c = b;
			$display("Blcoking : a = %d ,b = %d, c = %d." ,a,b,c);
		end
endmodule 

module non_blocking(clk,a,b,c);
	output 	[3:0] b,c;
	input 	[3:0] a;
	input		clk;
	reg [3:0] b,c;
always @(posedge clk)
 begin
	b <= a;
	c <= b;
	$display("Non_Blocking: a = %d, b = %d, c = %d.",a,b,c);
 end
 endmodule 

    Testbench:

`timescale 1 ns / 100 ps 
`include "C:/*****/blocking.v"
`include "C:/*****/non_blocking.v"
//前面两个include中填入上述两个module的文件地址
module compareTop;
	wire  [3:0] b1,c1,b2,c2;
	reg	[3:0] a;
	reg 		 clk;
	
	initial 
	begin 
		clk = 0;
		forever #50 clk = ~clk;	//frequency = 10M
	end
	
	initial
	begin