【FPGA】【Verilog】【基础模块】状态机

        结果：

module seq(ans,clk,reset,x,in);
	input clk,reset,x,in;
	output ans;
	reg [3:0] state;
	reg ans;
	
	
	parameter IDLE='d0;
	parameter  A='d1;
	parameter B='d2;
	parameter C='d3;
	parameter D ='d4;
	parameter E ='d5;
	
	always @(posedge clk)
		if(!reset)
			begin 
				state <= IDLE;
			end
		else 
			casex(state)
				IDLE : if (in == 1)
							begin 
									state <= A;
							end
						 else
									state <= IDLE;
					A: if (x == 1)
							begin 
									state <= B;
							end
					B: if (x == 1)
				      	begin 
									state <= C;
							end
						 else 
								state <= A;
					C: if (x == 1)
				      	begin 
									state <= D;
							end
						 else 
								state <= A;
					D: if (x == 1)
				      	begin 
									state <= E;
							end
						 else 
								state <=  A;
					E: if (x == 1)
				      	begin 
									ans <= 1'b1;
							end
			 default: state = IDLE;
			endcase 
	endmodule 

        Testbench:

                当数据包含连续的4个以上的1时：

`timescale 1 ns / 1 ns 
`include"C:/**********/seq.v"

module seqdet_Top;
	reg clk,rst;
	reg [15:0] data;
	wire ans;
	wire x,in;
	reg ans_out;

	assign x = data[15];
	assign in = 1;
	
	always #10 clk = ~clk;
	always @(posedge clk)
			data = {data[14:0],data[15]};
	
	initial 
		begin 
			clk = 0;
			rst = 1;
			#50 rst = 0;
			#50 rst = 1;
			data = 'b1_00111_11011_00100;
			#1000 $stop;
		end
	seq m(
	.ans(ans),
	.clk(clk),
	.reset(rst),
	.x(x),
	.in(in)
	);
	
	always @(posedge clk)
		case(ans)
			1: ans_out <= 1;
			default: ans_out <= 0;
		endcase 
	
endmodule 

                仿真波形:

            当数据不包含连续的4个以上的1时：

            

`timescale 1 ns / 1 ns 
`include"C:/**********/seq.v"

module seqdet_Top;
	reg clk,rst;
	reg [15:0] data;
	wire ans;
	wire x,in;
	reg ans_out;

	assign x = data[15];
	assign in = 1;
	
	always #10 clk = ~clk;
	always @(posedge clk)
			data = {data[14:0],data[15]};
	
	initial 
		begin 
			clk = 0;
			rst = 1;
			#50 rst = 0;
			#50 rst = 1;
			data = 'b1_10110_11011_00100;
			#1000 $stop;
		end
	seq m(
	.ans(ans),
	.clk(clk),
	.reset(rst),
	.x(x),
	.in(in)
	);
	
	always @(posedge clk)
		case(ans)
			1: ans_out <= 1;
			default: ans_out <= 0;
		endcase 
	
endmodule 

                   仿真波