单时钟:
八位DATA,八位地址时:
Testbench:
`timescale 1ns/1ns
`define clk_period 20
module dpram_tb;
reg clock;
reg [7:0]data;
reg [7:0]rdaddress;
reg [7:0]wraddress;
reg wren;
wire [7:0]q;
integer i;
dpram dpram0(
.clock(clock),
.data(data),
.rdaddress(rdaddress),
.wraddress(wraddress),
.wren(wren),
.q(q)
);
initial clock = 1;
always#(`clk_period/2)clock = ~clock; //50Mhz t = 20ns
initial begin
data = 0;
rdaddress = 30;
wraddress = 0;
wren = 0;
#(`clk_period*20 +1 );
for (i=0;i<=15;i=i+1)begin
wren = 1; //写使能
data = 255 - i;//生成DATA
wraddress = i; //地址和i的变化相同
#`clk_period; //延时一个时钟
end
wren = 0; //读状态
#(`clk_period*20);
for (i=0;i<=15;i=i