Vitis HLS入门指南

简介：本文是2022 Xilinx FPGA冬令营学习笔记

视频链接： 2022冬令营Vitis HLS入门指南

参考：ug1399 （vitis HLS synthesis user guide）

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Design principle

吞吐量throughput：the number of specific actions executed per unit of time or results produced per unit of time

性能Performance: higer throughput with low power consumption

Three paradigms for programming FPGAs

生产者范式 producer and consumer paradigm

生产者在处理过程中，消费者完全在等待，降低了性能

只要是1producer和1consumer，就可以采用FIFO或者PIPO（ping-pong buffer）来实现。