目录
2.1.7 Declaring wires(Wire decl)
2.2.2 Vectors in more detail(Vector1)
2.2.3 Vector part select(Vector2)
2.2.4 Bitwise operators(Vectorgates)
2.2.5 Four-input gates(Gates4)
2.2.6 Vector concatenation operator(Vector3)
2.2.7 Vector reversal 1(Vectorr)
2.2.8 Replication operation(Vector4)
2.2.9 More replication(Vector5)
前言
HDLbits的题目已经做完好久了,为了更好的巩固学习内容,从今天开始此博客每天更新系列答案,有些题目可能有多种方法, 博主会把自己的方法都写出来。如果有部分题目难一些的话,博主会给出自己的说明,同学们如果发现代码有错误的地方,欢迎大家留言指出来,博主会尽快改正。希望能和大家一起学习,一起进步。
1 Getting Started
1.1 Getting Started(Step one)
module top_module( output one );
// Insert your code here
assign one = 1'b1;
endmodule
1.2 Output Zero(Zero)
module top_module(
output zero
);// Module body starts after semicolon
assign zero = 1'b0;
endmodule
2 Verilog Language
2.1 Basics
2.1.1 Simple wire(wire)
module top_module( input in, output out );
assign out = in;
endmodule
2.1.2 Four wires(wire4)
module top_module(
input a,b,c,
output w,x,y,z );
assign w = a;
assign x = b;
assign y = b;
assign z = c;
endmodule
2.1.3 Inverter(Notgate)
module top_module( input in, output out );
assign out = ~in;
//second way
//not(out, in);
endmodule
2.1.4 AND gate(Andgate)
module top_module(
input a,
input b,
output out );
assign out = a & b;
//second way
//and(out, a, b);
endmodule
2.1.5 NOR gate (Norgate)
module top_module(
input a,
input b,
output out );
assign out = ~(a | b);
endmodule
2.1.6 XNOR gate(Xnorgate)
module top_module(
input a,
input b,
output out );
assign out = a ~^ b;
//second way
//assign out = a ^~ b;
//third way
//assign out = ~(a ^ b);
endmodule
2.1.7 Declaring wires(Wire decl)
module top_module(
input a,
input b,
input c,
input d,
output out,
output out_n );
wire w1;
wire w2;
assign w1 = a & b;
assign w2 = c & d;
assign out = w1 | w2;
assign out_n = ~(w1 | w2);
//second way
//assign out = a & b | c & d;
//assign out_n = ~(a & b | c & d);
endmodule
2.1.8 7458 chip(7458)
module top_module (
input p1a, p1b, p1c, p1d, p1e, p1f,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = p1a & p1b & p1c | p1d & p1e & p1f;
assign p2y = p2a & p2b | p2c & p2d;
endmodule
2.2 Vectors
2.2.1 Vectors(Vector0)
module top_module (
input wire [2:0] vec,
output wire [2:0] outv,
output wire o2,
output wire o1,
output wire o0 ); // Module body starts after module declaration
assign outv = vec;
assign o2 = vec[2];
assign o1 = vec[1];
assign o0 = vec[0];
//second way
//assign outv = vec;
//assign {o2, o1, o0} = vec;
endmodule
2.2.2 Vectors in more detail(Vector1)
module top_module(
input wire [15:0] in,
output wire [7:0] out_hi,
output wire [7:0] out_lo );
assign out_hi = in[15:8];
assign out_lo = in[7:0];
//second way
//assign {out_hi, out_lo} = in;
endmodule
2.2.3 Vector part select(Vector2)
module top_module(
input [31:0] in,
output [31:0] out );//
assign out = {in[7:0], in[15:8], in[23:16], in[31:24]};
//second way
//assign out[31:24] = in[7:0];
//assign out[23:16] = in[15:8];
//assign out[15:8] = in[23:16];
//assign out[7:0] = in[31:24];
endmodule
2.2.4 Bitwise operators(Vectorgates)
module top_module(
input [2:0] a,
input [2:0] b,
output [2:0] out_or_bitwise,
output out_or_logical,
output [5:0] out_not
);
assign out_or_bitwise = a | b;
assign out_or_logical = a || b;
assign out_not[2:0] = ~a;
assign out_not[5:3] = ~b;
endmodule
2.2.5 Four-input gates(Gates4)
module top_module(
input [3:0] in,
output out_and,
output out_or,
output out_xor
);
assign out_and = & in;
assign out_or = | in;
assign out_xor = ^ in;
endmodule
2.2.6 Vector concatenation operator(Vector3)
module top_module (
input [4:0] a, b, c, d, e, f,
output [7:0] w, x, y, z );//
assign {w, x, y, z} = {a, b, c, d, e, f, 2'b11};
endmodule
2.2.7 Vector reversal 1(Vectorr)
module top_module(
input [7:0] in,
output [7:0] out
);
generate
genvar i;
for(i = 0; i <= 7; i = i + 1)begin:conv
assign out[i] = in[7-i];
end
endgenerate
//second way
/*
integer i;
always@(*)begin
for(i = 0; i <= 7; i = i + 1)begin
out[i] = in[7-i];
end
end
*/
//third way
//assign out = {in[0], in[1], in[2], in[3], in[4], in[5], in[6], in[7]};
endmodule
2.2.8 Replication operation(Vector4)
module top_module (
input [7:0] in,
output [31:0] out );//
assign out = {{24{in[7]}}, in};
//second way
//assign out = in[7] ? {{24{1'b1}}, in} : {{24{1'b0}}, in};
endmodule
2.2.9 More replication(Vector5)
module top_module (
input a, b, c, d, e,
output [24:0] out );//
assign out = {{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}} ~^ {5{a, b, c, d, e}};
// second way
/*
wire [24:0] in1;
wire [24:0] in2;
assign in1 = {{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}};
assign in2 = {5{a, b, c, d, e}};
assign out = in1 ~^ in2;
*/
//third way
/*
assign out = {{a ~^ a}, {a ~^ b}, {a ~^ c}, {a ~^ d}, {a ~^ e},
{b ~^ a}, {b ~^ b}, {b ~^ c}, {b ~^ d}, {b ~^ e},
{c ~^ a}, {c ~^ b}, {c ~^ c}, {c ~^ d}, {c ~^ e},
{d ~^ a}, {d ~^ b}, {d ~^ c}, {d ~^ d}, {d ~^ e},
{e ~^ a}, {e ~^ b}, {e ~^ c}, {e ~^ d}, {e ~^ e}};
*/
endmodule
结语
今天先更新这三个小节吧,开始的内容相对基础,适合用来巩固。