fpga电平约束有什么作用_请问我将引脚电压电平约束到lvcmos25的含义是什么？

最新推荐文章于 2024-07-19 16:56:41 发布

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最新推荐文章于 2024-07-19 16:56:41 发布

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文章标签： fpga电平约束有什么作用

本文链接：https://blog.csdn.net/weixin_29957761/article/details/114497663

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FPGA电平约束LVCMOS25是指承诺为该引脚所在bank的Vcco供电2.5V。这确保FPGA提供2.5V LVCMOS逻辑电平。如果不匹配，会影响输出时序、驱动电流、输出电压和输入阈值。LVCMOS标准相对于Vcco定义，输出驱动依赖于Vcco，而输入阈值与Vcco成比例。不正确的Vcco可能导致驱动电流过多或不足。

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以上来自于谷歌翻译

以下为原文

For most FPGA families there will be a "SelectIO User's Guide" which describes in detail the various IO standards and what Vcco is required (if any) for that standard. Most output standards require a specific Vcco because this powers the drivers. Some input standards can work with any Vcco as long as the input signal is not clamped. That's because in some cases the input receivers are powered by VccAux.

All LVCMOS standards are defined relative to Vcco. The outputs drive to the rails. The input thresholds are ratiometric to Vcco. It's important to let the tools know the correct standards you will be using so that they can prevent you from placing incompatible IO standards in the same bank. If your Vcco does not match the requirements of the standard, the IO will not work as expected. For LVCMOS this includes:

1) Timing. Output delays will differ from the timing reports if the Vcco doesn't match the requirement for the standard.

2) Drive current. The drive current and output impedance will not match the specs. Usually a higher Vcco will result in lower impedance and higher drive current.

3) Output voltage. As I said, the outputs drive to the rails. So the output high voltage will follow Vcco regardless of the LVCMOS standard used.

4) Input threshold.

One note on output driver implementation. LVCMOS outputs use a set of output FETs which can