下面是一个示例的 RTL (register-transfer level) 代码,用来生成 PWM (pulse width modulation) 时序:
module pwm_generator(
input clk,
input rst,
input [7:0] duty_cycle,
output reg pwm_out
);
reg [15:0] counter;
always @(posedge clk) begin
if (rst) begin
counter <= 0;