此代码是8b10b解码的verilog实现代码,非查表代码。即rx端的解码。
此代码在项目中,已经使用多次,相当成熟。
module 8b10b_decode (datain, dispin, dataout, dispout, code_err, disp_err) ;
input wire [9:0] datain ;
input wire dispin ;
output wire [8:0] dataout ;
output wire dispout ;
output wire code_err ;
output wire disp_err ;
wire ai = datain[0] ;
wire bi = datain[1] ;
wire ci = datain[2] ;
wire di = datain[3] ;
wire ei = datain[4] ;
wire ii = datain[5] ;
wire fi = datain[6] ;
wire gi = datain[7] ;
wire hi = datain[8] ;
wire ji = datain[9] ;
转载:https://blog.csdn.net/weixin_36590806/article/details/111059629
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wire aeqb = (ai & bi) | (!ai & !bi) ;
wire ceqd = (ci & di) | (!ci & !di) ;
wire p22 = (ai & bi & !ci & !di) |
(ci & di & !ai & !bi) |
( !aeqb & !ceqd) ;
wire p13 = ( !aeqb & !ci & !di) |
( !ceqd & !ai & !bi) ;
wire p31 = ( !aeqb & ci & di) |
( !ceqd & ai & bi) ;
wire p40 = ai & bi & ci &